do_adc.vhd

rs422协议的通讯程序.做一些简单改动即可以移植到各种环境。

--功能：读出AD值.
--输入：sa=x"c001"
--      启动命令：x"01" = 单独启动CH指定的一路。
--              " x"07" = 从ch=0开始连续启动5路。           
--	  	sa=x"c000" 通道号：ch
--
--输出：如果是测+5V参考电压，则给出好与不好。
--	    如果是连通性检查，则给出连通否。
--      如果是SD，则给出当前SD位置。
--      如果是CM，则给出当前CM位置。
--返回状态：sa=x"c018"
--			adc_st=x"80"  正常结束。
--          adc_st="00"   复位 
--          adc_st=x"03"  AD未正常结束，超时。

LIBRARY IEEE;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity do_adc is port(
		rst				: in std_logic;
		sa				: in std_logic_vector(15 downto 0);
		ad_in			: in std_logic_vector(7 downto 0);
		iow				: in std_logic;
		p12mhz			: in std_logic;
		cda				: out std_logic_vector(2 downto 0);
		eoc_state		: in std_logic;
		sd				: in std_logic_vector(7 downto 0);
		rd_adl			: out std_logic;
		rd_adh			: out std_logic;
		start_ad 		: out std_logic;
	--ad 转换状态。00=转换结束；11=转换超时。	
		adc_state		: out std_logic_vector(7 downto 0);
		lchk_level 		: out std_logic_vector(1 downto 0); 
		p28v_level 		: out std_logic;
		n28v_level 		: out std_logic;
		ref5v_level		: out std_logic;	
		cm_level 		: out std_logic_vector(3 downto 0);
		sd_level		: out std_logic_vector(2 downto 0);
		x_ad_data		: out std_logic_vector(11 downto 0)
);
end entity ;

architecture ad of do_adc is

component wri_reg8 is port(
		iow			: in std_logic;
		rst			: in std_logic;
		cs			: in std_logic;
		data_in		: in std_logic_vector(7 downto 0);
		data_out	: out std_logic_vector(7 downto 0)
		);
end component;
		
component sig_adc is port(
		rst				: in std_logic;
		sa				: in std_logic_vector(15 downto 0);
		ad_in			: in std_logic_vector(7 downto 0);
		can_adc			: in std_logic;
		iow				: in std_logic;
		p12mhz			: in std_logic;
		eoc_state		: in std_logic;
		sd				: in std_logic_vector(7 downto 0);
		rd_adl			: out std_logic;
		rd_adh			: out std_logic;
		start_ad 		: out std_logic;
	--ad 转换状态。00=转换结束；11=转换超时。	
		adc_state		: out std_logic_vector(7 downto 0);
		ad_data			: out std_logic_vector(11 downto 0)


);
end component;
	
signal st : integer range 0 to 20;
		
constant st_idle 					: integer	:= 0;
constant st_start_con_adc			: integer	:= 1;	
constant st_start_con_adc_wait		: integer	:= 2;
constant st_start_con_adc_wait0		: integer	:= 3;
constant st_start_con_adc_wait1		: integer	:= 4;
constant st_start_con_adc_next		: integer	:= 5;
constant st_adc_end					: integer	:= 6;
constant st_adc_end_wait			: integer	:= 7;
constant st_read_adc_data			: integer	:= 8;
constant st_adc_error				: integer	:= 9;
constant st_start_con_adc_next1		: integer	:= 10;
constant st_start_con_adc_wait1x	: integer	:= 11;
constant st_start_con_adc_wait1x0	: integer	:= 12;
-----------------------------------------------------
constant st_y7b_adc					: integer	:= 13;
constant st_y7b_adc_wait			: integer	:= 14;
constant st_y7b_adc_wait0			: integer	:= 15;
constant st_y7b_adc_wait1x0			: integer	:= 16;
constant st_y7b_adc_wait1x			: integer	:= 17;
constant st_read_y7b_adc_data		: integer	:= 18;
constant st_y7b_adc_wait1			: integer	:= 19;
------------------------------------------------------

----lchk--如果小于clhk,则未开锁---
--未开锁时，输入电压2.58V，开锁后，输入电压为5.6V
	
	

constant no_lock_l 	: std_logic_vector(11 downto 0) := x"890";--1.75V
constant no_lock_h 	: std_logic_vector(11 downto 0) := x"966";--3.50V
constant on_lock_l 	: std_logic_vector(11 downto 0) := x"A30";--5.00V
constant on_lock_h 	: std_logic_vector(11 downto 0) := x"ACC";--6.25V
constant no_y7b 	: std_logic_vector(11 downto 0) := x"fff";--17.5V
-------------cm1 data-----------------------
constant cml1 : std_logic_vector(11 downto 0) := x"920";
constant cmh1 : std_logic_vector(11 downto 0) := x"a65";
-------------cm2 data-----------------------
constant cml2 : std_logic_vector(11 downto 0) := x"a66";
constant cmh2 : std_logic_vector(11 downto 0) := x"b99";
-------------cm3 data-----------------------
constant cml3 : std_logic_vector(11 downto 0) := x"b9A";
constant cmh3 : std_logic_vector(11 downto 0) := x"CCC";
-------------cm4 data-----------------------
constant cml4 : std_logic_vector(11 downto 0) := x"CCD";
constant cmh4 : std_logic_vector(11 downto 0) := x"ECC";
-------------cm5 data-----------------------
constant cml5 : std_logic_vector(11 downto 0) := x"ECD";
constant cmh5 : std_logic_vector(11 downto 0) := x"fff";
-------------cm6 data-----------------------
constant cml6 : std_logic_vector(11 downto 0) := x"534";
constant cmh6 : std_logic_vector(11 downto 0) := x"665";
-------------cm7 data-----------------------
constant cml7 : std_logic_vector(11 downto 0) := x"666";
constant cmh7 : std_logic_vector(11 downto 0) := x"733";
-------------cm8 data-----------------------
constant cml8 : std_logic_vector(11 downto 0) := x"401";
constant cmh8 : std_logic_vector(11 downto 0) := x"533";
-------------cm9 data-----------------------
constant cml9 : std_logic_vector(11 downto 0) := x"334";
constant cmh9 : std_logic_vector(11 downto 0) := x"400";
-------------cm1 data-----------------------
constant cml10 : std_logic_vector(11 downto 0) := x"201";
constant cmh10 : std_logic_vector(11 downto 0) := x"333";
-------------cm11 data-----------------------
constant cml11 : std_logic_vector(11 downto 0) := x"000";
constant cmh11 : std_logic_vector(11 downto 0) := x"133";
-------------cm1 data-----------------------
constant cml12 : std_logic_vector(11 downto 0) := x"134";
constant cmh12 : std_logic_vector(11 downto 0) := x"200";


-------------sd data----------------------- 
-------sd1---------
constant sdl1 : std_logic_vector(11 downto 0) := x"900";
constant sdh1 : std_logic_vector(11 downto 0) := x"9e0";
-------sd2---------
constant sdl2 : std_logic_vector(11 downto 0) := x"9e1";
constant sdh2 : std_logic_vector(11 downto 0) := x"ae0";
-------sd3---------
constant sdl3 : std_logic_vector(11 downto 0) := x"ae1";
constant sdh3 : std_logic_vector(11 downto 0) := x"be0";
-------sd4----------
constant sdl4 : std_logic_vector(11 downto 0) := x"be1";
constant sdh4 : std_logic_vector(11 downto 0) := x"ce0";
-------sd5----------
constant sdl5 : std_logic_vector(11 downto 0) := x"ce1";
constant sdh5 : std_logic_vector(11 downto 0) := x"de0";
-------sd6----------
constant sdl6 : std_logic_vector(11 downto 0) := x"de1";
constant sdh6 : std_logic_vector(11 downto 0) := x"ee0";
-------sd7----------
constant sdl7 : std_logic_vector(11 downto 0) := x"ee1";
constant sdh7 : std_logic_vector(11 downto 0) := x"fff";

-----------ad_data_P28-------------
constant p28v_l : std_logic_vector(11 downto 0) := x"f90";
constant p28v_h : std_logic_vector(11 downto 0) := x"fff";
-----------ad_data_n28-------------
constant n28v_h : std_logic_vector(11 downto 0) := x"066";
constant n28v_l : std_logic_vector(11 downto 0) := x"000";
-------------ref5v---------------
constant ref5v_l : std_logic_vector(11 downto 0) := x"B90";--4.5V
constant ref5v_h : std_logic_vector(11 downto 0) := x"c70";--5.5V
---------------channel limit-----------
constant channel_limit : integer := 6;

--channel
signal cs_t_ch : std_logic;
signal t_cda : std_logic_vector(7 downto 0);
signal t_ch : std_logic_vector(7 downto 0);
----------------------------------------
signal ad_data_lchk : std_logic_vector(11 downto 0);
signal ad_data_sd : std_logic_vector(11 downto 0);
signal ad_data_cm : std_logic_vector(11 downto 0);
signal ad_data_P28 : std_logic_vector(11 downto 0);
signal ad_data_N28 : std_logic_vector(11 downto 0);
signal ad_data_V5 : std_logic_vector(11 downto 0);
signal ad_temp : std_logic_vector(11 downto 0);
signal t_adc_state : std_logic_vector(7 downto 0);
signal t_read_ch : std_logic_vector(7 downto 0); 
---------sig_ad data---------------------------
-----根据各个通道，判决输入状态。
--如果lchk_level="11",则+28VB未连接，
--    lchk_level="01",则未开锁。
--    lchk_level="10",则已开锁。
signal t_lchk_level : std_logic_vector(1 downto 0); 
--共1-7级
signal t_sd_level : std_logic_vector(2 downto 0);
--共1-12级
signal t_cm_level : std_logic_vector(3 downto 0);

--测p28v。经变压后成9.5V以上。
--如果电压在9.5V，则p28_level='0',否则='1'.
signal t_p28v_level : std_logic;

--测n28v。经变压后成0.5V以下。
--如果电压在0.5V以下，则n28_level='0',否则='1'.
signal t_n28v_level : std_logic;

--测ref5v。如果电压在4.5V~5.5V，则ref5v_level='0',否则='1'。
signal t_ref5v_level : std_logic; 

----------启动ad
signal t_sig_adc : std_logic;
signal t_ad_data : std_logic_vector(11 downto 0);
signal t_can_con_adc : std_logic;
signal t_can_con_adc_end : std_logic;

begin


--选择通道号，读AD值。
cs_t_ch <= '0' when sa=x"c000" else '1';
u_sel_read_ch : wri_reg8 port map(
		iow			=> iow,--: in std_logic;
		rst			=> rst,--: in std_logic;
		cs			=> cs_t_ch,--: in std_logic;
		data_in		=> ad_in,--: in std_logic_vector(7 downto 0);
		data_out	=> t_ch--: out std_logic_vector(7 downto 0)
		);