cpu.map.rpt

rs422协议的通讯程序.做一些简单改动即可以移植到各种环境。

; read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|data_clk ; 20      ;
; tx8:u_tx8|data_clk:u_data_clk|data_clk                             ; 7       ;
; do_adc:u_ad|t_sig_adc                                              ; 1       ;
; rx8:u_rx8|data_clk:u_data_clk|data_clk                             ; 16      ;
; read_return_pre_set:u_rx_tx|t_rst_rx                               ; 2       ;
; Total number of inverted registers = 11                            ;         ;
+--------------------------------------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Fri Dec 14 13:47:11 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off cpu -c cpu
Info: Found 2 design units, including 1 entities, in source file rx8.vhd
    Info: Found design unit 1: rx8-rx
    Info: Found entity 1: rx8
Info: Found 2 design units, including 1 entities, in source file tx16.vhd
    Info: Found design unit 1: tx16-tx
    Info: Found entity 1: tx16
Info: Found 2 design units, including 1 entities, in source file rx16.vhd
    Info: Found design unit 1: rx16-rx
    Info: Found entity 1: rx16
Info: Found 2 design units, including 1 entities, in source file data_clk.vhd
    Info: Found design unit 1: data_clk-clk
    Info: Found entity 1: data_clk
Info: Found 2 design units, including 1 entities, in source file gen_1mhz.vhd
    Info: Found design unit 1: gen_1mhz-gen_clk
    Info: Found entity 1: gen_1mhz
Info: Found 2 design units, including 1 entities, in source file cpu.vhd
    Info: Found design unit 1: cpu-cpu
    Info: Found entity 1: cpu
Info: Found 2 design units, including 1 entities, in source file wri_reg8.vhd
    Info: Found design unit 1: wri_reg8-wri_reg8
    Info: Found entity 1: wri_reg8
Info: Found 2 design units, including 1 entities, in source file writeLED_and_tx.vhd
    Info: Found design unit 1: writeLED_and_tx-writeLED_and_tx
    Info: Found entity 1: writeLED_and_tx
Info: Found 2 design units, including 1 entities, in source file get_key_from_rx.vhd
    Info: Found design unit 1: get_key_from_rx-get_set_rx
    Info: Found entity 1: get_key_from_rx
Info: Found 2 design units, including 1 entities, in source file exm_self.vhd
    Info: Found design unit 1: exm_self-exm
    Info: Found entity 1: exm_self
Info: Found 2 design units, including 1 entities, in source file do_adc.vhd
    Info: Found design unit 1: do_adc-ad
    Info: Found entity 1: do_adc
Info: Found 2 design units, including 1 entities, in source file read_return_pre_set.vhd
    Info: Found design unit 1: read_return_pre_set-read_return
    Info: Found entity 1: read_return_pre_set
Info: Found 2 design units, including 1 entities, in source file sig_adc.vhd
    Info: Found design unit 1: sig_adc-ad
    Info: Found entity 1: sig_adc
Info: Found 2 design units, including 1 entities, in source file time_out.vhd
    Info: Found design unit 1: time_out-time
    Info: Found entity 1: time_out
Info: Found 2 design units, including 1 entities, in source file generate_int.vhd
    Info: Found design unit 1: generate_int-int
    Info: Found entity 1: generate_int
Info: Found 2 design units, including 1 entities, in source file timer.vhd
    Info: Found design unit 1: timer-timer
    Info: Found entity 1: timer
Info: Found 2 design units, including 1 entities, in source file tx8.vhd
    Info: Found design unit 1: tx8-tx
    Info: Found entity 1: tx8
Info: Found 2 design units, including 1 entities, in source file write_reg.vhd
    Info: Found design unit 1: write_reg-write
    Info: Found entity 1: write_reg
Info: VHDL Case Statement information at rx8.vhd(109): OTHERS choice is never selected
Warning: Reduced register "do_adc:u_ad|st[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_out:u_time_out|y7b_time_out_tag[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_out:u_time_out|y7b_time_out_tag[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_out:u_time_out|sec1_time_out_tag[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_out:u_time_out|sec1_time_out_tag[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_out:u_time_out|y7b_time_out_tag[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_out:u_time_out|y7b_time_out_tag[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_out:u_time_out|sec1_time_out_tag[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "time_out:u_time_out|sec1_time_out_tag[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "do_adc:u_ad|adc_state[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "do_adc:u_ad|adc_state[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "do_adc:u_ad|adc_state[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "do_adc:u_ad|adc_state[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "do_adc:u_ad|sig_adc:u_sig_adc|adc_state[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "do_adc:u_ad|sig_adc:u_sig_adc|adc_state[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "do_adc:u_ad|sig_adc:u_sig_adc|adc_state[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "do_adc:u_ad|sig_adc:u_sig_adc|adc_state[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "do_adc:u_ad|sig_adc:u_sig_adc|adc_state[2]" with stuck data_in port to stuck value GND
Info: Inferred 10 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "read_return_pre_set:u_rx_tx|tx16:u_tx|data_cnt[0]~5"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "do_adc:u_ad|t_cda[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "tx8:u_tx8|data_cnt[0]~5"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "read_return_pre_set:u_rx_tx|rx16:u_rx|data_cnt[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: "gen_1mhz:u_p1mhz|p1khz_cnt[0]~9"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=7) from the following logic: "timer:U_TIMER|t_hour_cnt[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "gen_1mhz:u_p1mhz|P1MHz_clk_cnt[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: "time_out:u_time_out|sec1_time_out_cnt[0]~10"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "rx8:u_rx8|data_cnt[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: "time_out:u_time_out|y7b_time_out_cnt[0]~11"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Duplicate registers merged to single register
    Info: Duplicate register "do_adc:u_ad|sig_adc:u_sig_adc|adc_state[0]" merged to single register "do_adc:u_ad|sig_adc:u_sig_adc|adc_state[1]"
    Info: Duplicate register "do_adc:u_ad|adc_state[3]" merged to single register "do_adc:u_ad|adc_state[7]"
    Info: Duplicate register "time_out:u_time_out|sec1_time_out_tag[3]" merged to single register "time_out:u_time_out|sec1_time_out_tag[7]"
    Info: Duplicate register "time_out:u_time_out|sec1_time_out_tag[6]" merged to single register "time_out:u_time_out|sec1_time_out_tag[7]"
    Info: Duplicate register "time_out:u_time_out|sec1_time_out_tag[2]" merged to single register "time_out:u_time_out|sec1_time_out_tag[7]"
    Info: Duplicate register "time_out:u_time_out|y7b_time_out_tag[0]" merged to single register "time_out:u_time_out|y7b_time_out_tag[5]"
    Info: Duplicate register "time_out:u_time_out|y7b_time_out_tag[1]" merged to single register "time_out:u_time_out|y7b_time_out_tag[5]"
    Info: Duplicate register "time_out:u_time_out|y7b_time_out_tag[4]" merged to single register "time_out:u_time_out|y7b_time_out_tag[5]"
    Info: Duplicate register "do_adc:u_ad|adc_state[0]" merged to single register "do_adc:u_ad|adc_state[1]"
Warning: TRI or OPNDRN buffers permanently disabled
    Warning: Node "p10~1"
    Warning: Node "p11~0"
    Warning: Node "p12~0"
    Warning: Node "p13~0"
    Warning: Node "p14~0"
    Warning: Node "p15~0"
    Warning: Node "p16~0"
    Warning: Node "p17~0"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SEL_eeprom_eprom" stuck at VCC
    Warning: Pin "rd_pesudo_key" stuck at GND
    Warning: Pin "EEPROM_IOW" stuck at GND
    Warning: Pin "EEPROM_IOR" stuck at GND
Info: Registers with preset signals will power-up high
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "sel"
Info: Implemented 1253 device resources after synthesis - the final resource count might be different
    Info: Implemented 29 input pins
    Info: Implemented 56 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 1160 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 34 warnings
    Info: Processing ended: Fri Dec 14 13:47:26 2007
    Info: Elapsed time: 00:00:15