rx16.vhd

rs422协议的通讯程序.做一些简单改动即可以移植到各种环境。

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity rx16 is port(
		rst				: in std_logic;
		p1mhz			: in std_logic;
		rx				: in std_logic;
		data_out		: out std_logic_vector(15 downto 0);
		rx_tag			: out std_logic;
		rst_rx			: in std_logic
);
end entity	;

architecture rx of rx16 is
		
component data_clk is port (
		rst				: in std_logic;
		p1mhz			: in std_logic;
		can_data_clk	: in std_logic;
		data_clk		: out std_logic		
);
end component;

signal data_cnt : integer range 0 to 31;
constant data_cnt_limit : integer := 18; 

signal rx_clk : std_logic;
signal beg_rx,end_rx : std_logic;
signal en_rx,en_rx_end : std_logic;
-----------------------------------
signal t_data : std_logic_vector(17 downto 0);
signal t_rx_tag : std_logic;

begin	


u_data_clk : data_clk port map(
		rst				=> rst,--: in std_logic;
		p1mhz			=> p1mhz,--: in std_logic;
		can_data_clk	=> en_rx,--: in std_logic;
		data_clk		=> rx_clk);--: out std_logic--;
	

stup_en_rx :process(rst,rx,en_rx_end)
begin
	if rst='0' or en_rx_end='1' then
		en_rx <= '0';
	else
		if falling_edge(rx) then
			if data_cnt=0 then
			 	en_rx <= '1';
			end if;
		end if;
	end if;		
end process;

gen_write_data_cnt : process(rst,en_rx,rx_clk) 
begin
	if rst='0' or en_rx='0' then
		en_rx_end <= '0';
		data_cnt <= 0;
	else
		if rising_edge(rx_clk) then	
			if en_rx = '1' and data_cnt < data_cnt_limit then
				data_cnt <= data_cnt + 1;
			else
				en_rx_end <= '1';	
			end if;
		end if;
	end if;			
end process;

write_data : process(rst,rx_clk,rx)
begin
	if rst='0' then
		t_data <= (others=>'0');
	else
		if falling_edge(rx_clk) then
			if en_rx = '1' then
				t_data(data_cnt)  <= rx;
			end if;
		end if;
	end if;		
end process;


process(rst,rst_rx,en_rx)
begin
	if rst='0' or rst_rx='0' then
		t_rx_tag <= '0';	
	else
		if falling_edge(en_rx) then	
			if t_data(0)='0' and t_data(17)='1' then
				t_rx_tag <= '1';
			end if;	
		end if;
	end if;		
end process;

rx_tag <= t_rx_tag;
data_out <= t_data(16 downto 1)  ;


end architecture ;