conv3.vhd

Program to implement convolution through VHDL...

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:13:11 02/27/2009 
-- Design Name: 
-- Module Name:    conv3 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

package integervector is
type int_vector is array(natural range <>) of natural range 0 to 255;
end;
use work.integervector.all;

entity conv3 is
port(x:in int_vector(0 to 1);
     clk:in bit;
     h:in int_vector(0 to 3);
     load:in bit;
     y:out int_vector(0 to 4));
end;
architecture blah of conv3 is
signal temp:int_vector(0 to 4) := (others => 0);
signal shiftreg:int_vector(0 to 4);
signal counter:integer range 0 to 3 := 0;
begin
     process(clk,load)
	  --variable shiftreg:int_vector(0 to 4);
     --variable counter:integer range 0 to 3 := 0;
	  begin
          if load='1' then
                 shiftreg(0 to 3)<= h(0 to 3);
                 shiftreg(4) <= 0;
          elsif(clk'event and clk='1') then
                 if counter<2 then
                    for i in 0 to 4 loop
                        temp(i) <= temp(i)+shiftreg(i)*x(counter);
                    end loop;
                    for j in 3 downto 0 loop
                        shiftreg(j+1) <= shiftreg(j);                 
                    end loop;
						  shiftreg(0) <= 0;
                    counter <= counter+1;
                 end if;
          end if;
     end process;
	  y <= temp;
end;