conv2.vhd

Program to implement convolution of two signals.

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:29:34 02/19/2009 
-- Design Name: 
-- Module Name:    conv2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

package integermath is
       type int_vector is array (integer range <>) of natural range 0 to 255;
end;

use work.integermath.all;

entity conv2 is
port(x:in int_vector(0 to 3);
     clk:in bit;
     h:in int_vector(0 to 3);
     load:in bit;
     y:out int_vector(0 to 3));
end;
architecture blah of conv2 is
signal shiftreg:int_vector(0 to 3);
signal temp:int_vector(0 to 3);
signal counter:integer range 0 to 7 := 0;
begin
      process(clk,load)
		--variable temp:int_vector(0 to 4);
		--variable shiftreg: int_vector(0 to 2);
      begin
           if load='1' then
               shiftreg(0 to 3) <= h(0 to 3);
           elsif (clk'event and clk = '1') then
                 if counter<4 then
                     for i in 0 to 3 loop
                         temp(i) <= temp(i)+shiftreg(i)*x(i);
                     end loop;
                     for j in 0 to 2 loop
							    shiftreg(j+1) <= shiftreg(j);                    
                     end loop;
							shiftreg(0) <= 0;
                     counter <= counter+1;
                 end if;
          end if;
      end process;
		y <= temp;
end;