encode2_10.vhd

来自「VHDL语言描述的二进制十进制译码电路」· VHDL 代码 · 共 12 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 entity encode2_10 is 
   port (
           a: in std_logic_vector ( 15 downto 0);
           b: out integer; )
end entity;
architecture v of encode2_10 is