multiplier.vhd

VHDL经典设计

--multiplier.vhd n-bit multiplier
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity multiplier is
generic ( n : integer := 7; nn : integer := 14 ) ;
port (	
  clock	: in std_logic ;--clock
  la : in std_logic ;--load of multiplicand
  lb : in std_logic ;--load of multiplier
  s	: in std_logic ;--start
  dataa	: in std_logic_vector(n-1 downto 0) ;--multiplicand
  datab	: in std_logic_vector(n-1 downto 0) ;--multiplier
  p	: buffer std_logic_vector(nn-1 downto 0) ;--porduct
  done : out std_logic ) ;
end multiplier ;
architecture behavior of multiplier is
  type state_type is ( s1, s2, s3 ) ;--state define
  signal y : state_type ;--state declaration
  signal psel: std_logic ;--select line of multiplexer
  signal z : std_logic ;--detecter of zero 
  signal ea : std_logic ;--enable of shift-left register(multiplicand)
  signal eb : std_logic ;--enable of shift-right register(multiplier)
  signal ep : std_logic ;--enable of product register
  signal zero : std_logic ;--series input of shift
  signal b : std_logic_vector(n-1 downto 0) ;--output of shift-right register
  signal n_zeros : std_logic_vector(n-1 downto 0) ;--n-bit zero load into register with multiplicand
  signal a : std_logic_vector(nn-1 downto 0) ;--output of shift-left register
  signal ain : std_logic_vector(nn-1 downto 0) ;--input of shift-left regster
  signal datap : std_logic_vector(nn-1 downto 0) ;--output of multiplexer 
  signal sum : std_logic_vector(nn-1 downto 0) ;--sum of product and multiplicand
  signal nn_zeros : std_logic_vector(nn-1 downto 0) ;--2*n-bit zero input to multiplicand
  signal q : integer range 0 to n;--count of downcounter
  signal ec : std_logic;--enable of downcounter
  signal lc : std_logic;--load of downcounter
begin
  fsm_transitions: process ( clock )
  begin
	if (clock'event and clock = '1') then
      case y is
	    when s1 =>
		  if s = '0' then	y <= s1 ; else y <= s2 ; end if ;
		when s2 =>
		  if z = '0' then y <= s2 ; else y <= s3 ; end if ;
		when s3 =>
		  if s = '1' then y <= s3 ; else y <= s1 ; end if ;
		end case ;
	end if ;
  end process ;

  fsm_outputs: process ( y, s, la, lb, b(0) )
  begin
    ep <= '0' ; ea <= '0' ; eb <= '0' ; done <= '0' ; psel <= '0';
    case y is
	  when s1 =>
		ep <= '1' ;
		if s = '0' and la = '1' then ea <= '1' ; 
		else ea <= '0' ; end if ;
		if s = '0' and lb = '1' then eb <= '1' ; 
		else eb <= '0' ; end if ;
	  when s2 =>
		ea <= '1' ; eb <= '1' ; psel <= '1' ;
		if b(0) = '1' then ep <= '1' ; else	ep <= '0' ; end if ;
	  when s3 =>
		done <= '1' ;
	  end case ;
	end process ;

  -- define the datapath circuit
  nn_zeros <= (others => '0' ) ;--2*n-bit zero
  n_zeros <= (others => '0' ) ;--n-bit zero
  zero <= '0' ;
  ain <= n_zeros & dataa ;
  shifta: shiftlne generic map ( n => nn )
	port map ( ain, la, ea, zero, clock, a ) ;

  shiftb: shiftrne generic map ( n => n )
	port map ( datab, lb, eb, zero, clock, b ) ;
  ec <= '1' ; lc <= not s;
  count: downcnt	generic map (n+1) port map(clock,ec,lc,q);
  z <= '1' when q = 0 else '0' ;
	
  sum <= a + p ;
  -- define the 2n 2-to-1 multiplexers for datap
  muxi: mux2to1 generic map ( n => nn ) 
    port map ( nn_zeros, sum, psel, datap ) ;
  regp: regne generic map ( n => nn )
	port map ( datap, ep, clock, p ) ;
end behavior ;