timer_cout.v

来自「ep2c5 实现 定时器 verilog语言」· Verilog 代码 · 共 87 行

module Timer_Cout(
					clk,
					rst_n,
									
					hour_H,
					hour_L,
					min_H,
					min_L
				);
			
input clk;
input rst_n;

output [2:0]min_H;
output [3:0]min_L;
output [1:0] hour_H;
output [3:0] hour_L; 

reg [2:0]min_H;
reg [3:0]min_L;	
reg	[1:0] hour_H;   // high
reg	[3:0] hour_L;   // low	

/*--------------------------------------------------------------------------*/

		always@(posedge clk or negedge rst_n)
			begin				
				if (~rst_n)
					begin
						min_L <= 4'd0;
						min_H <= 3'd0;

					end
				else
					begin
						if (min_L == 4'd9)
							begin
								min_L <= 4'd0;
								min_H <= (min_H == 3'd5) ? 3'd0 : (min_H + 3'd1);				
							end
												
						else
							begin
								min_L <= min_L + 4'd1;
							end
					end
			end 

/*--------------------------------------------------------------------------*/

		always@(posedge clk or negedge rst_n)
			begin
				if (~rst_n)
					begin
						hour_L <= 4'd0;
						hour_H <= 2'd0;
					end
				else
					begin		
						if ((min_H == 3'd5) && (min_L == 4'd9))
							begin
								if (hour_H == 2'd2)
									begin
										hour_L <= (hour_L == 4'd3) ? 4'd0 : (hour_L + 4'd1);
										
										if (hour_L == 4'd3)
											begin
												hour_H <= 2'd0;
											end
									end
								else
									begin
										hour_L <= (hour_L == 4'd9) ? 4'd0 : (hour_L + 4'd1);
										
										if (hour_L == 4'd9)
											begin
												hour_H <= hour_H + 2'd1;
											end					
									end
							end
					end
			end
			
/*--------------------------------------------------------------------------*/
			
			
endmodule