timer.map.summary

来自「ep2c5 实现 定时器 verilog语言」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Wed Jul 02 22:13:37 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : Timer
Top-level Entity Name : Timer
Family : Cyclone II
Total logic elements : 77
    Total combinational functions : 77
    Dedicated logic registers : 68
Total registers : 68
Total pins : 18
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0