basegate.v.bak

ep2c5 实现 逻辑门 verilog语言

module BaseGate(
					Sw_n,
					Led_En_n,
					Led
				);

input [3:0] Sw_n;

output Led_En_n;
output [7:0] Led;

	assign 
		Led_En_n = 1'd0;

	assign 
		Led[0] = ~Sw_n[1] | ~Sw_n[0],
		Led[7:1] = 7'd0;
	
endmodule