timer.fit.qmsg

来自「Verilog 下脉冲发生器的源代码」· QMSG 代码 · 共 32 行 · 第 1/2 页

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.335 ns register register " "Info: Estimated most critical path is register to register delay of 7.335 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[16\] 1 REG LAB_X48_Y13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X48_Y13; Fanout = 3; REG Node = 'cnt\[16\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[16] } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.473 ns) + CELL(0.150 ns) 0.623 ns Equal0~231 2 COMB LAB_X48_Y13 1 " "Info: 2: + IC(0.473 ns) + CELL(0.150 ns) = 0.623 ns; Loc. = LAB_X48_Y13; Fanout = 1; COMB Node = 'Equal0~231'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.623 ns" { cnt[16] Equal0~231 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(0.150 ns) 1.379 ns Equal0~232 3 COMB LAB_X47_Y13 14 " "Info: 3: + IC(0.606 ns) + CELL(0.150 ns) = 1.379 ns; Loc. = LAB_X47_Y13; Fanout = 14; COMB Node = 'Equal0~232'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.756 ns" { Equal0~231 Equal0~232 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.437 ns) 1.943 ns Equal0~235 4 COMB LAB_X47_Y13 5 " "Info: 4: + IC(0.127 ns) + CELL(0.437 ns) = 1.943 ns; Loc. = LAB_X47_Y13; Fanout = 5; COMB Node = 'Equal0~235'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.564 ns" { Equal0~232 Equal0~235 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.672 ns) + CELL(0.414 ns) 4.029 ns Add0~193 5 COMB LAB_X42_Y26 2 " "Info: 5: + IC(1.672 ns) + CELL(0.414 ns) = 4.029 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~193'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.086 ns" { Equal0~235 Add0~193 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.100 ns Add0~195 6 COMB LAB_X42_Y26 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 4.100 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~195'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~193 Add0~195 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.171 ns Add0~197 7 COMB LAB_X42_Y26 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 4.171 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~197'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~195 Add0~197 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.242 ns Add0~199 8 COMB LAB_X42_Y26 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 4.242 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~199'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~197 Add0~199 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.313 ns Add0~201 9 COMB LAB_X42_Y26 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 4.313 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~201'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~199 Add0~201 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.384 ns Add0~203 10 COMB LAB_X42_Y26 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 4.384 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~203'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~201 Add0~203 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.455 ns Add0~205 11 COMB LAB_X42_Y26 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.455 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~205'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~203 Add0~205 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.526 ns Add0~207 12 COMB LAB_X42_Y26 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 4.526 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~207'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~205 Add0~207 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.597 ns Add0~209 13 COMB LAB_X42_Y26 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.597 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~209'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~207 Add0~209 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.668 ns Add0~211 14 COMB LAB_X42_Y26 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 4.668 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~211'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~209 Add0~211 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.739 ns Add0~213 15 COMB LAB_X42_Y26 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 4.739 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~213'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~211 Add0~213 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.810 ns Add0~215 16 COMB LAB_X42_Y26 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 4.810 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~215'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~213 Add0~215 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.881 ns Add0~217 17 COMB LAB_X42_Y26 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 4.881 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~217'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~215 Add0~217 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.952 ns Add0~219 18 COMB LAB_X42_Y26 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 4.952 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~219'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~217 Add0~219 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.023 ns Add0~221 19 COMB LAB_X42_Y26 1 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 5.023 ns; Loc. = LAB_X42_Y26; Fanout = 1; COMB Node = 'Add0~221'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~219 Add0~221 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 5.433 ns Add0~222 20 COMB LAB_X42_Y26 2 " "Info: 20: + IC(0.000 ns) + CELL(0.410 ns) = 5.433 ns; Loc. = LAB_X42_Y26; Fanout = 2; COMB Node = 'Add0~222'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add0~221 Add0~222 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.398 ns) 6.149 ns Equal3~165 21 COMB LAB_X43_Y26 1 " "Info: 21: + IC(0.318 ns) + CELL(0.398 ns) = 6.149 ns; Loc. = LAB_X43_Y26; Fanout = 1; COMB Node = 'Equal3~165'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.716 ns" { Add0~222 Equal3~165 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.410 ns) 6.686 ns Equal3~169 22 COMB LAB_X43_Y26 2 " "Info: 22: + IC(0.127 ns) + CELL(0.410 ns) = 6.686 ns; Loc. = LAB_X43_Y26; Fanout = 2; COMB Node = 'Equal3~169'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.537 ns" { Equal3~165 Equal3~169 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.275 ns) 7.251 ns flag_b~26 23 COMB LAB_X43_Y26 1 " "Info: 23: + IC(0.290 ns) + CELL(0.275 ns) = 7.251 ns; Loc. = LAB_X43_Y26; Fanout = 1; COMB Node = 'flag_b~26'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { Equal3~169 flag_b~26 } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.335 ns flag_b 24 REG LAB_X43_Y26 3 " "Info: 24: + IC(0.000 ns) + CELL(0.084 ns) = 7.335 ns; Loc. = LAB_X43_Y26; Fanout = 3; REG Node = 'flag_b'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { flag_b~26 flag_b } "NODE_NAME" } } { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.722 ns ( 50.74 % ) " "Info: Total cell delay = 3.722 ns ( 50.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.613 ns ( 49.26 % ) " "Info: Total interconnect delay = 3.613 ns ( 49.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.335 ns" { cnt[16] Equal0~231 Equal0~232 Equal0~235 Add0~193 Add0~195 Add0~197 Add0~199 Add0~201 Add0~203 Add0~205 Add0~207 Add0~209 Add0~211 Add0~213 Add0~215 Add0~217 Add0~219 Add0~221 Add0~222 Equal3~165 Equal3~169 flag_b~26 flag_b } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x33_y24 x43_y36 " "Info: The peak interconnect region extends from location x33_y24 to location x43_y36" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "4 " "Warning: Found 4 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "a 0 " "Info: Pin \"a\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "out_a 0 " "Info: Pin \"out_a\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "out_b 0 " "Info: Pin \"out_b\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "out_c 0 " "Info: Pin \"out_c\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 21 20:29:39 2007 " "Info: Processing ended: Sat Apr 21 20:29:39 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/code/verilog/svc_timer33ms/timer.fit.smsg " "Info: Generated suppressed messages file E:/code/verilog/svc_timer33ms/timer.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}