timer.map.qmsg

Verilog 下脉冲发生器的源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 21 20:29:17 2007 " "Info: Processing started: Sat Apr 21 20:29:17 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off timer -c timer " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off timer -c timer" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer " "Info: Found entity 1: timer" {  } { { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "timer " "Info: Elaborating entity \"timer\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 timer.v(21) " "Warning (10230): Verilog HDL assignment warning at timer.v(21): truncated value with size 32 to match size of target (16)" {  } { { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 timer.v(24) " "Warning (10230): Verilog HDL assignment warning at timer.v(24): truncated value with size 32 to match size of target (21)" {  } { { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 timer.v(46) " "Warning (10230): Verilog HDL assignment warning at timer.v(46): truncated value with size 32 to match size of target (21)" {  } { { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 timer.v(66) " "Warning (10230): Verilog HDL assignment warning at timer.v(66): truncated value with size 32 to match size of target (21)" {  } { { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 timer.v(89) " "Warning (10230): Verilog HDL assignment warning at timer.v(89): truncated value with size 32 to match size of target (21)" {  } { { "timer.v" "" { Text "E:/code/verilog/svc_timer33ms/timer.v" 89 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "295 " "Info: Implemented 295 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "289 " "Info: Implemented 289 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 21 20:29:20 2007 " "Info: Processing ended: Sat Apr 21 20:29:20 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}