timer.v.bak

Verilog 下脉冲发生器的源代码

module timer (clk,rst,a,out_a,out_b,out_c);  //50MHz
   input clk,rst;
   output a,out_a,out_b,out_c;
   reg a,out_a,out_b,out_c;
   reg [20:0]cnt;
   reg [20:0] cnt_a,cnt_b,cnt_c;
   reg flag_b,flag_c;
   reg [15:0]cnt_temp;
   always @(posedge clk) //clk=50MHz
     begin
		 if(rst==0)     //低电平复位,高电平正常工作
			 begin
				a=1;
				cnt_temp=0;flag_b=0;flag_c=0;cnt=0;
			 end
		 else 
			 begin
				 if(cnt==166666)  //3.3ms 166667
					begin
						cnt=0;
						if(cnt_temp==3050)    //10s
							cnt_temp=3050;
						else
							cnt_temp=cnt_temp+1;
					end
		 		else 
					cnt=cnt+1;
		 		if(cnt==0)
					a=0;
		 		else if(cnt==50000)   //1ms
					begin
						a=1;
					end
				if(cnt_temp==1)
					flag_c=1;
				if(cnt_temp==2)
					flag_b=1;
				if(cnt_temp==3050)
					a=1;
	 		end
		end
   always @(posedge clk)
     begin
		if(rst==0)   //低电平复位
			begin out_a=1;cnt_a=0;end
		else
			begin
          		if(cnt_a==500000)   //10ms
			  		cnt_a=0;
		  		else 
					cnt_a=cnt_a+1;
		 		if(cnt_a==0)
					out_a=0; 
		 		else if(cnt_a==50000)
					out_a=1;
				if(cnt_temp==3050)
					out_a=1;
     		end
		end
  always @(posedge clk)
    begin
		if(rst==0)   //低电平复位
			begin out_b=1;cnt_b=0;end
        else
			begin
				if(flag_b==1)
					begin
						if(cnt_b==500000)
							cnt_b=0;
						else 
							cnt_b=cnt_b+1;
						if(cnt_b==0)
							out_b=0;
						else if(cnt_b==50000)
							out_b=1;
					end
				else
					out_b=1;
        		if(cnt_temp==3050)
					out_b=1;
			end
	end
   always @(posedge clk)
    begin
		if(rst==0)   //低电平复位
			begin out_c=1;cnt_c=0;end
		else
			begin
        		if(flag_c==1)
					begin
						if(cnt_c==500000)
							cnt_c=0;
						else 
							cnt_c=cnt_c+1;
						if(cnt_c==0)
							out_c=0;
						else if(cnt_c==50000)
							out_c=1;
					end
				else
					out_c=1;
				if(cnt_temp==3050)
					out_c=1;
			end

    end

endmodule