timer.qsf

Verilog 下脉冲发生器的源代码

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		timer_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY timer
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:48:50  SEPTEMBER 13, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V
set_global_assignment -name END_TIME "70 ms"
set_global_assignment -name GLITCH_INTERVAL "0 ns"
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN "0 ns"
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_location_assignment PIN_K26 -to a
set_location_assignment PIN_N2 -to clk
set_location_assignment PIN_M20 -to out_a
set_location_assignment PIN_M25 -to out_b
set_location_assignment PIN_R24 -to out_c
set_location_assignment PIN_N25 -to rst
set_global_assignment -name VERILOG_FILE timer.v
set_global_assignment -name SIMULATION_MODE FUNCTIONAL