timer.map.rpt

Verilog 下脉冲发生器的源代码

; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                              ;
+----------------------------------+-----------------+------------------------+---------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path          ;
+----------------------------------+-----------------+------------------------+---------------------------------------+
; timer.v                          ; yes             ; User Verilog HDL File  ; E:/code/verilog/svc_timer33ms/timer.v ;
+----------------------------------+-----------------+------------------------+---------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 289   ;
; Total combinational functions               ; 289   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 83    ;
;     -- 3 input functions                    ; 34    ;
;     -- <=2 input functions                  ; 172   ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 194   ;
;     -- arithmetic mode                      ; 95    ;
; Total registers                             ; 106   ;
; I/O pins                                    ; 6     ;
; Maximum fan-out node                        ; rst   ;
; Maximum fan-out                             ; 108   ;
; Total fan-out                               ; 1037  ;
; Average fan-out                             ; 2.59  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |timer                     ; 289 (289)         ; 106 (106)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 6    ; 0            ; |timer              ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 106   ;
; Number of registers using Synchronous Clear  ; 2     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 42    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 21 bits   ; 42 LEs        ; 21 LEs               ; 21 LEs                 ; Yes        ; |timer|cnt_b[3]            ;
; 3:1                ; 21 bits   ; 42 LEs        ; 21 LEs               ; 21 LEs                 ; Yes        ; |timer|cnt_c[4]            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Apr 21 20:29:17 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off timer -c timer
Info: Found 1 design units, including 1 entities, in source file timer.v
    Info: Found entity 1: timer
Info: Elaborating entity "timer" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at timer.v(21): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at timer.v(24): truncated value with size 32 to match size of target (21)
Warning (10230): Verilog HDL assignment warning at timer.v(46): truncated value with size 32 to match size of target (21)
Warning (10230): Verilog HDL assignment warning at timer.v(66): truncated value with size 32 to match size of target (21)
Warning (10230): Verilog HDL assignment warning at timer.v(89): truncated value with size 32 to match size of target (21)
Info: Implemented 295 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 4 output pins
    Info: Implemented 289 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Sat Apr 21 20:29:20 2007
    Info: Elapsed time: 00:00:04