pwm.tan.qmsg

FPGA下PWM的Verilog 源码

{ "Info" "ITDB_TH_RESULT" "amp_sanjiao\[0\] reset pll_clk -2.900 ns register " "Info: th for register \"amp_sanjiao\[0\]\" (data pin = \"reset\", clock pin = \"pll_clk\") is -2.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_clk destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"pll_clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pll_clk 1 CLK PIN_184 46 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 46; CLK Node = 'pll_clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll_clk } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns amp_sanjiao\[0\] 2 REG LC75 28 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC75; Fanout = 28; REG Node = 'amp_sanjiao\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { pll_clk amp_sanjiao[0] } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 311 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk amp_sanjiao[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out amp_sanjiao[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 311 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns reset 1 PIN PIN_128 53 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_128; Fanout = 53; PIN Node = 'reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.200 ns) 5.900 ns amp_sanjiao\[0\] 2 REG LC75 28 " "Info: 2: + IC(3.000 ns) + CELL(2.200 ns) = 5.900 ns; Loc. = LC75; Fanout = 28; REG Node = 'amp_sanjiao\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.200 ns" { reset amp_sanjiao[0] } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 311 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 49.15 % ) " "Info: Total cell delay = 2.900 ns ( 49.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 50.85 % ) " "Info: Total interconnect delay = 3.000 ns ( 50.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { reset amp_sanjiao[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.900 ns" { reset reset~out amp_sanjiao[0] } { 0.000ns 0.000ns 3.000ns } { 0.000ns 0.700ns 2.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk amp_sanjiao[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out amp_sanjiao[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { reset amp_sanjiao[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.900 ns" { reset reset~out amp_sanjiao[0] } { 0.000ns 0.000ns 3.000ns } { 0.000ns 0.700ns 2.200ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 14 19:58:18 2007 " "Info: Processing ended: Thu Jun 14 19:58:18 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}