pwm.tan.qmsg

FPGA下PWM的Verilog 源码

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "pll_clk " "Info: Assuming node \"pll_clk\" is an undefined clock" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 3 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pll_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "pll_clk register sin_cnt\[8\] register amp_sin1\[3\] 30.96 MHz 32.3 ns Internal " "Info: Clock \"pll_clk\" has Internal fmax of 30.96 MHz between source register \"sin_cnt\[8\]\" and destination register \"amp_sin1\[3\]\" (period= 32.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.900 ns + Longest register register " "Info: + Longest register to register delay is 28.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sin_cnt\[8\] 1 REG LC142 49 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC142; Fanout = 49; REG Node = 'sin_cnt\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_cnt[8] } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.700 ns) 6.100 ns sin_cnt~502 2 COMB SEXP51 8 " "Info: 2: + IC(3.400 ns) + CELL(2.700 ns) = 6.100 ns; Loc. = SEXP51; Fanout = 8; COMB Node = 'sin_cnt~502'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { sin_cnt[8] sin_cnt~502 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 7.100 ns sin_cnt~606 3 COMB LC51 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 7.100 ns; Loc. = LC51; Fanout = 1; COMB Node = 'sin_cnt~606'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { sin_cnt~502 sin_cnt~606 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 7.500 ns sin_cnt~608 4 COMB LC52 1 " "Info: 4: + IC(0.000 ns) + CELL(0.400 ns) = 7.500 ns; Loc. = LC52; Fanout = 1; COMB Node = 'sin_cnt~608'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { sin_cnt~606 sin_cnt~608 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 7.900 ns sin_cnt~614 5 COMB LC53 1 " "Info: 5: + IC(0.000 ns) + CELL(0.400 ns) = 7.900 ns; Loc. = LC53; Fanout = 1; COMB Node = 'sin_cnt~614'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { sin_cnt~608 sin_cnt~614 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 10.100 ns sin_cnt~509 6 COMB LC54 215 " "Info: 6: + IC(0.000 ns) + CELL(2.200 ns) = 10.100 ns; Loc. = LC54; Fanout = 215; COMB Node = 'sin_cnt~509'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { sin_cnt~614 sin_cnt~509 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(2.700 ns) 17.400 ns WideOr15~3518 7 COMB SEXP192 2 " "Info: 7: + IC(4.600 ns) + CELL(2.700 ns) = 17.400 ns; Loc. = SEXP192; Fanout = 2; COMB Node = 'WideOr15~3518'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.300 ns" { sin_cnt~509 WideOr15~3518 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 18.400 ns WideOr15~3480 8 COMB LC178 1 " "Info: 8: + IC(0.000 ns) + CELL(1.000 ns) = 18.400 ns; Loc. = LC178; Fanout = 1; COMB Node = 'WideOr15~3480'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { WideOr15~3518 WideOr15~3480 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 20.600 ns WideOr15~3393 9 COMB LC179 4 " "Info: 9: + IC(0.000 ns) + CELL(2.200 ns) = 20.600 ns; Loc. = LC179; Fanout = 4; COMB Node = 'WideOr15~3393'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { WideOr15~3480 WideOr15~3393 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.700 ns) 26.300 ns Selector5~8 10 COMB SEXP15 2 " "Info: 10: + IC(3.000 ns) + CELL(2.700 ns) = 26.300 ns; Loc. = SEXP15; Fanout = 2; COMB Node = 'Selector5~8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { WideOr15~3393 Selector5~8 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 27.300 ns Selector5~24 11 COMB LC3 1 " "Info: 11: + IC(0.000 ns) + CELL(1.000 ns) = 27.300 ns; Loc. = LC3; Fanout = 1; COMB Node = 'Selector5~24'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { Selector5~8 Selector5~24 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 28.900 ns amp_sin1\[3\] 12 REG LC4 3 " "Info: 12: + IC(0.000 ns) + CELL(1.600 ns) = 28.900 ns; Loc. = LC4; Fanout = 3; REG Node = 'amp_sin1\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { Selector5~24 amp_sin1[3] } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.900 ns ( 61.94 % ) " "Info: Total cell delay = 17.900 ns ( 61.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.000 ns ( 38.06 % ) " "Info: Total interconnect delay = 11.000 ns ( 38.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "28.900 ns" { sin_cnt[8] sin_cnt~502 sin_cnt~606 sin_cnt~608 sin_cnt~614 sin_cnt~509 WideOr15~3518 WideOr15~3480 WideOr15~3393 Selector5~8 Selector5~24 amp_sin1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "28.900 ns" { sin_cnt[8] sin_cnt~502 sin_cnt~606 sin_cnt~608 sin_cnt~614 sin_cnt~509 WideOr15~3518 WideOr15~3480 WideOr15~3393 Selector5~8 Selector5~24 amp_sin1[3] } { 0.000ns 3.400ns 0.000ns 0.000ns 0.000ns 0.000ns 4.600ns 0.000ns 0.000ns 3.000ns 0.000ns 0.000ns } { 0.000ns 2.700ns 1.000ns 0.400ns 0.400ns 2.200ns 2.700ns 1.000ns 2.200ns 2.700ns 1.000ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"pll_clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pll_clk 1 CLK PIN_184 46 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 46; CLK Node = 'pll_clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll_clk } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns amp_sin1\[3\] 2 REG LC4 3 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC4; Fanout = 3; REG Node = 'amp_sin1\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { pll_clk amp_sin1[3] } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk amp_sin1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out amp_sin1[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"pll_clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pll_clk 1 CLK PIN_184 46 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 46; CLK Node = 'pll_clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll_clk } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns sin_cnt\[8\] 2 REG LC142 49 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC142; Fanout = 49; REG Node = 'sin_cnt\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { pll_clk sin_cnt[8] } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk sin_cnt[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out sin_cnt[8] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk amp_sin1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out amp_sin1[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk sin_cnt[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out sin_cnt[8] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.100 ns + " "Info: + Micro setup delay of destination is 2.100 ns" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "28.900 ns" { sin_cnt[8] sin_cnt~502 sin_cnt~606 sin_cnt~608 sin_cnt~614 sin_cnt~509 WideOr15~3518 WideOr15~3480 WideOr15~3393 Selector5~8 Selector5~24 amp_sin1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "28.900 ns" { sin_cnt[8] sin_cnt~502 sin_cnt~606 sin_cnt~608 sin_cnt~614 sin_cnt~509 WideOr15~3518 WideOr15~3480 WideOr15~3393 Selector5~8 Selector5~24 amp_sin1[3] } { 0.000ns 3.400ns 0.000ns 0.000ns 0.000ns 0.000ns 4.600ns 0.000ns 0.000ns 3.000ns 0.000ns 0.000ns } { 0.000ns 2.700ns 1.000ns 0.400ns 0.400ns 2.200ns 2.700ns 1.000ns 2.200ns 2.700ns 1.000ns 1.600ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk amp_sin1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out amp_sin1[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk sin_cnt[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out sin_cnt[8] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "amp_sin1\[3\] div_con\[1\] pll_clk 26.800 ns register " "Info: tsu for register \"amp_sin1\[3\]\" (data pin = \"div_con\[1\]\", clock pin = \"pll_clk\") is 26.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "27.100 ns + Longest pin register " "Info: + Longest pin to register delay is 27.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns div_con\[1\] 1 PIN PIN_70 144 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_70; Fanout = 144; PIN Node = 'div_con\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { div_con[1] } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(1.000 ns) 5.100 ns sin_cnt~635 2 COMB LC129 1 " "Info: 2: + IC(3.400 ns) + CELL(1.000 ns) = 5.100 ns; Loc. = LC129; Fanout = 1; COMB Node = 'sin_cnt~635'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.400 ns" { div_con[1] sin_cnt~635 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 5.500 ns sin_cnt~637 3 COMB LC130 1 " "Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 5.500 ns; Loc. = LC130; Fanout = 1; COMB Node = 'sin_cnt~637'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { sin_cnt~635 sin_cnt~637 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 5.900 ns sin_cnt~643 4 COMB LC131 1 " "Info: 4: + IC(0.000 ns) + CELL(0.400 ns) = 5.900 ns; Loc. = LC131; Fanout = 1; COMB Node = 'sin_cnt~643'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { sin_cnt~637 sin_cnt~643 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 8.100 ns sin_cnt~533 5 COMB LC132 260 " "Info: 5: + IC(0.000 ns) + CELL(2.200 ns) = 8.100 ns; Loc. = LC132; Fanout = 260; COMB Node = 'sin_cnt~533'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { sin_cnt~643 sin_cnt~533 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.800 ns) + CELL(2.700 ns) 15.600 ns WideOr13~2557 6 COMB SEXP186 11 " "Info: 6: + IC(4.800 ns) + CELL(2.700 ns) = 15.600 ns; Loc. = SEXP186; Fanout = 11; COMB Node = 'WideOr13~2557'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { sin_cnt~533 WideOr13~2557 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 16.600 ns WideOr15~3480 7 COMB LC178 1 " "Info: 7: + IC(0.000 ns) + CELL(1.000 ns) = 16.600 ns; Loc. = LC178; Fanout = 1; COMB Node = 'WideOr15~3480'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { WideOr13~2557 WideOr15~3480 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 18.800 ns WideOr15~3393 8 COMB LC179 4 " "Info: 8: + IC(0.000 ns) + CELL(2.200 ns) = 18.800 ns; Loc. = LC179; Fanout = 4; COMB Node = 'WideOr15~3393'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { WideOr15~3480 WideOr15~3393 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.700 ns) 24.500 ns Selector5~8 9 COMB SEXP15 2 " "Info: 9: + IC(3.000 ns) + CELL(2.700 ns) = 24.500 ns; Loc. = SEXP15; Fanout = 2; COMB Node = 'Selector5~8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { WideOr15~3393 Selector5~8 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 25.500 ns Selector5~24 10 COMB LC3 1 " "Info: 10: + IC(0.000 ns) + CELL(1.000 ns) = 25.500 ns; Loc. = LC3; Fanout = 1; COMB Node = 'Selector5~24'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { Selector5~8 Selector5~24 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 27.100 ns amp_sin1\[3\] 11 REG LC4 3 " "Info: 11: + IC(0.000 ns) + CELL(1.600 ns) = 27.100 ns; Loc. = LC4; Fanout = 3; REG Node = 'amp_sin1\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { Selector5~24 amp_sin1[3] } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.900 ns ( 58.67 % ) " "Info: Total cell delay = 15.900 ns ( 58.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.200 ns ( 41.33 % ) " "Info: Total interconnect delay = 11.200 ns ( 41.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "27.100 ns" { div_con[1] sin_cnt~635 sin_cnt~637 sin_cnt~643 sin_cnt~533 WideOr13~2557 WideOr15~3480 WideOr15~3393 Selector5~8 Selector5~24 amp_sin1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "27.100 ns" { div_con[1] div_con[1]~out sin_cnt~635 sin_cnt~637 sin_cnt~643 sin_cnt~533 WideOr13~2557 WideOr15~3480 WideOr15~3393 Selector5~8 Selector5~24 amp_sin1[3] } { 0.000ns 0.000ns 3.400ns 0.000ns 0.000ns 0.000ns 4.800ns 0.000ns 0.000ns 3.000ns 0.000ns 0.000ns } { 0.000ns 0.700ns 1.000ns 0.400ns 0.400ns 2.200ns 2.700ns 1.000ns 2.200ns 2.700ns 1.000ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.100 ns + " "Info: + Micro setup delay of destination is 2.100 ns" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_clk destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"pll_clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pll_clk 1 CLK PIN_184 46 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 46; CLK Node = 'pll_clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll_clk } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns amp_sin1\[3\] 2 REG LC4 3 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC4; Fanout = 3; REG Node = 'amp_sin1\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { pll_clk amp_sin1[3] } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 308 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk amp_sin1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out amp_sin1[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "27.100 ns" { div_con[1] sin_cnt~635 sin_cnt~637 sin_cnt~643 sin_cnt~533 WideOr13~2557 WideOr15~3480 WideOr15~3393 Selector5~8 Selector5~24 amp_sin1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "27.100 ns" { div_con[1] div_con[1]~out sin_cnt~635 sin_cnt~637 sin_cnt~643 sin_cnt~533 WideOr13~2557 WideOr15~3480 WideOr15~3393 Selector5~8 Selector5~24 amp_sin1[3] } { 0.000ns 0.000ns 3.400ns 0.000ns 0.000ns 0.000ns 4.800ns 0.000ns 0.000ns 3.000ns 0.000ns 0.000ns } { 0.000ns 0.700ns 1.000ns 0.400ns 0.400ns 2.200ns 2.700ns 1.000ns 2.200ns 2.700ns 1.000ns 1.600ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk amp_sin1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out amp_sin1[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "pll_clk pwm4 pwm3~reg0 10.500 ns register " "Info: tco from clock \"pll_clk\" to destination pin \"pwm4\" through register \"pwm3~reg0\" is 10.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"pll_clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns pll_clk 1 CLK PIN_184 46 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 46; CLK Node = 'pll_clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll_clk } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns pwm3~reg0 2 REG LC174 2 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC174; Fanout = 2; REG Node = 'pwm3~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { pll_clk pwm3~reg0 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 400 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk pwm3~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out pwm3~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 400 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns + Longest register pin " "Info: + Longest register to pin delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm3~reg0 1 REG LC174 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC174; Fanout = 2; REG Node = 'pwm3~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pwm3~reg0 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 400 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.800 ns) 5.800 ns pwm3~3 2 COMB LC67 1 " "Info: 2: + IC(3.000 ns) + CELL(2.800 ns) = 5.800 ns; Loc. = LC67; Fanout = 1; COMB Node = 'pwm3~3'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.800 ns" { pwm3~reg0 pwm3~3 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 6.800 ns pwm4 3 PIN PIN_153 0 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 6.800 ns; Loc. = PIN_153; Fanout = 0; PIN Node = 'pwm4'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { pwm3~3 pwm4 } "NODE_NAME" } } { "pwm.v" "" { Text "E:/code/verilog/lai_PWM/pwm.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns ( 55.88 % ) " "Info: Total cell delay = 3.800 ns ( 55.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 44.12 % ) " "Info: Total interconnect delay = 3.000 ns ( 44.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.800 ns" { pwm3~reg0 pwm3~3 pwm4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.800 ns" { pwm3~reg0 pwm3~3 pwm4 } { 0.000ns 3.000ns 0.000ns } { 0.000ns 2.800ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { pll_clk pwm3~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { pll_clk pll_clk~out pwm3~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.800 ns" { pwm3~reg0 pwm3~3 pwm4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.800 ns" { pwm3~reg0 pwm3~3 pwm4 } { 0.000ns 3.000ns 0.000ns } { 0.000ns 2.800ns 1.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}