pwm.tan.summary

FPGA下PWM的Verilog 源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 26.800 ns
From           : div_con[3]
To             : amp_sin1[3]
From Clock     : --
To Clock       : pll_clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.500 ns
From           : pwm1~reg0
To             : pwm2
From Clock     : pll_clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.900 ns
From           : reset
To             : amp_sanjiao[8]
From Clock     : --
To Clock       : pll_clk
Failed Paths   : 0

Type           : Clock Setup: 'pll_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 30.96 MHz ( period = 32.300 ns )
From           : sin_cnt[8]
To             : amp_sin1[3]
From Clock     : pll_clk
To Clock       : pll_clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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