del.v

FPGA下PWM的Verilog 源码

module del(clk,start,int1,int2,int3,int4,int5,int6,out1,out2,out3,out4,out5,out6) ;
  input clk,start,int1,int2,int3,int4,int5,int6;
  output out1,out2,out3,out4,out5,out6;
  reg out1,out2,out3,out4,out5,out6;
  always @(posedge clk or negedge start)
   begin 
   if(!start)
      begin
        out1=int1;
        out2=int2;
    	out3=int3;
    	out4=int4;
    	out5=int5;
    	out6=int6;
      end	
    end
  endmodule