📄 pwm.v
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module pwm(reset,pll_clk,div_con,,pwm1,pwm2,pwm3,pwm4);
input reset;
input pll_clk;
input [3:0] div_con; //分频控制
output pwm1,pwm2,pwm3,pwm4;
////测试///////////////////////////////
reg [10:0] amp_sin1,amp_sin2,amp_sin3;
reg pwm1,pwm2,pwm3,pwm4;
reg [10:0]amp_sanjiao;
reg flag_sanjiao; //上升还是下降 0--up,1--down
reg sign_sanjiao; //符号 0---posedge,1---负
reg pwm11,pwm22,pwm33,pwm44;
reg [9:0] sin_cnt;
reg flag_sin1,flag_sin2,flag_sin3;
reg [5:0] count;
reg [5:0] sys_cnt;
reg [5:0]temp_cnt;
//reg [5:0]temp_cnt2;
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//always @(posedge sys_clk) //正弦波模块,幅值256,每360个sys_clk为一个周期
always @(posedge pll_clk) //正弦波模块,幅值256,每360个sys_clk为一个周期
begin
//-----分频-------------------------
case (div_con)
0: begin count=17; end //F_sin=400M/(34*360)=32679
1: begin count=20; end //F_sin=400M/(40*360)=27777
2: begin count=25; end
3: begin count=30; end
4: begin count=35; end
5: begin count=40; end
default: count=45;
endcase
if(sys_cnt>count)
sys_cnt=0;
else if(sys_cnt==count)
begin
sys_cnt=0;
if(sin_cnt==179)
sin_cnt=0;
else
sin_cnt=sin_cnt+1;
end
else
sys_cnt=sys_cnt+1;
case (sin_cnt)
0: begin amp_sin1=128; end
1: begin amp_sin1=131; end
2: begin amp_sin1=134; end
3: begin amp_sin1=137; end
4: begin amp_sin1=141; end
5: begin amp_sin1=144; end
6: begin amp_sin1=147; end
7: begin amp_sin1=150; end
8: begin amp_sin1=153; end
9: begin amp_sin1=156; end
10: begin amp_sin1=159; end
11: begin amp_sin1=162; end
12: begin amp_sin1=165; end
13: begin amp_sin1=168; end
14: begin amp_sin1=171; end
15: begin amp_sin1=174; end
16: begin amp_sin1=177; end
17: begin amp_sin1=180; end
18: begin amp_sin1=183; end
19: begin amp_sin1=186; end
20: begin amp_sin1=188; end
21: begin amp_sin1=191; end
22: begin amp_sin1=194; end
23: begin amp_sin1=196; end
24: begin amp_sin1=199; end
25: begin amp_sin1=202; end
26: begin amp_sin1=204; end
27: begin amp_sin1=207; end
28: begin amp_sin1=209; end
29: begin amp_sin1=212; end
30: begin amp_sin1=214; end
31: begin amp_sin1=216; end
32: begin amp_sin1=219; end
33: begin amp_sin1=221; end
34: begin amp_sin1=223; end
35: begin amp_sin1=225; end
36: begin amp_sin1=227; end
37: begin amp_sin1=229; end
38: begin amp_sin1=231; end
39: begin amp_sin1=233; end
40: begin amp_sin1=234; end
41: begin amp_sin1=236; end
42: begin amp_sin1=238; end
43: begin amp_sin1=239; end
44: begin amp_sin1=241; end
45: begin amp_sin1=242; end
46: begin amp_sin1=244; end
47: begin amp_sin1=245; end
48: begin amp_sin1=246; end
49: begin amp_sin1=247; end
50: begin amp_sin1=249; end
51: begin amp_sin1=250; end
52: begin amp_sin1=250; end
53: begin amp_sin1=251; end
54: begin amp_sin1=252; end
55: begin amp_sin1=253; end
56: begin amp_sin1=254; end
57: begin amp_sin1=254; end
58: begin amp_sin1=255; end
59: begin amp_sin1=255; end
60: begin amp_sin1=255; end
61: begin amp_sin1=256; end
62: begin amp_sin1=256; end
63: begin amp_sin1=256; end
64: begin amp_sin1=256; end
65: begin amp_sin1=256; end
66: begin amp_sin1=256; end
67: begin amp_sin1=256; end
68: begin amp_sin1=255; end
69: begin amp_sin1=255; end
70: begin amp_sin1=255; end
71: begin amp_sin1=254; end
72: begin amp_sin1=254; end
73: begin amp_sin1=253; end
74: begin amp_sin1=252; end
75: begin amp_sin1=251; end
76: begin amp_sin1=250; end
77: begin amp_sin1=250; end
78: begin amp_sin1=249; end
79: begin amp_sin1=247; end
80: begin amp_sin1=246; end
81: begin amp_sin1=245; end
82: begin amp_sin1=244; end
83: begin amp_sin1=242; end
84: begin amp_sin1=241; end
85: begin amp_sin1=239; end
86: begin amp_sin1=238; end
87: begin amp_sin1=236; end
88: begin amp_sin1=234; end
89: begin amp_sin1=233; end
90: begin amp_sin1=231; end
91: begin amp_sin1=229; end
92: begin amp_sin1=227; end
93: begin amp_sin1=225; end
94: begin amp_sin1=223; end
95: begin amp_sin1=221; end
96: begin amp_sin1=219; end
97: begin amp_sin1=216; end
98: begin amp_sin1=214; end
99: begin amp_sin1=212; end
100: begin amp_sin1=209; end
101: begin amp_sin1=207; end
102: begin amp_sin1=204; end
103: begin amp_sin1=202; end
104: begin amp_sin1=199; end
105: begin amp_sin1=196; end
106: begin amp_sin1=194; end
107: begin amp_sin1=191; end
108: begin amp_sin1=188; end
109: begin amp_sin1=186; end
110: begin amp_sin1=183; end
111: begin amp_sin1=180; end
112: begin amp_sin1=177; end
113: begin amp_sin1=174; end
114: begin amp_sin1=171; end
115: begin amp_sin1=168; end
116: begin amp_sin1=165; end
117: begin amp_sin1=162; end
118: begin amp_sin1=159; end
119: begin amp_sin1=156; end
120: begin amp_sin1=153; end
121: begin amp_sin1=150; end
122: begin amp_sin1=147; end
123: begin amp_sin1=144; end
124: begin amp_sin1=141; end
125: begin amp_sin1=137; end
126: begin amp_sin1=134; end
127: begin amp_sin1=131; end
128: begin amp_sin1=128; end
129: begin amp_sin1=125; end
130: begin amp_sin1=122; end
131: begin amp_sin1=119; end
132: begin amp_sin1=115; end
133: begin amp_sin1=112; end
134: begin amp_sin1=109; end
135: begin amp_sin1=106; end
136: begin amp_sin1=103; end
137: begin amp_sin1=100; end
138: begin amp_sin1=97; end
139: begin amp_sin1=94; end
140: begin amp_sin1=91; end
141: begin amp_sin1=88; end
142: begin amp_sin1=85; end
143: begin amp_sin1=82; end
144: begin amp_sin1=79; end
145: begin amp_sin1=76; end
146: begin amp_sin1=73; end
147: begin amp_sin1=70; end
148: begin amp_sin1=68; end
149: begin amp_sin1=65; end
150: begin amp_sin1=62; end
151: begin amp_sin1=60; end
152: begin amp_sin1=57; end
153: begin amp_sin1=54; end
154: begin amp_sin1=52; end
155: begin amp_sin1=49; end
156: begin amp_sin1=47; end
157: begin amp_sin1=44; end
158: begin amp_sin1=42; end
159: begin amp_sin1=40; end
160: begin amp_sin1=37; end
161: begin amp_sin1=35; end
162: begin amp_sin1=33; end
163: begin amp_sin1=31; end
164: begin amp_sin1=29; end
165: begin amp_sin1=27; end
166: begin amp_sin1=25; end
167: begin amp_sin1=23; end
168: begin amp_sin1=22; end
169: begin amp_sin1=20; end
170: begin amp_sin1=18; end
171: begin amp_sin1=17; end
172: begin amp_sin1=15; end
173: begin amp_sin1=14; end
174: begin amp_sin1=12; end
175: begin amp_sin1=11; end
176: begin amp_sin1=10; end
177: begin amp_sin1=9; end
178: begin amp_sin1=7; end
179: begin amp_sin1=6; end
180: begin amp_sin1=6; end
181: begin amp_sin1=5; end
182: begin amp_sin1=4; end
183: begin amp_sin1=3; end
184: begin amp_sin1=2; end
185: begin amp_sin1=2; end
186: begin amp_sin1=1; end
187: begin amp_sin1=1; end
188: begin amp_sin1=1; end
189: begin amp_sin1=0; end
190: begin amp_sin1=0; end
191: begin amp_sin1=0; end
192: begin amp_sin1=0; end
193: begin amp_sin1=0; end
194: begin amp_sin1=0; end
195: begin amp_sin1=0; end
196: begin amp_sin1=1; end
197: begin amp_sin1=1; end
198: begin amp_sin1=1; end
199: begin amp_sin1=2; end
200: begin amp_sin1=2; end
201: begin amp_sin1=3; end
202: begin amp_sin1=4; end
203: begin amp_sin1=5; end
204: begin amp_sin1=6; end
205: begin amp_sin1=6; end
206: begin amp_sin1=7; end
207: begin amp_sin1=9; end
208: begin amp_sin1=10; end
209: begin amp_sin1=11; end
210: begin amp_sin1=12; end
211: begin amp_sin1=14; end
212: begin amp_sin1=15; end
213: begin amp_sin1=17; end
214: begin amp_sin1=18; end
215: begin amp_sin1=20; end
216: begin amp_sin1=22; end
217: begin amp_sin1=23; end
218: begin amp_sin1=25; end
219: begin amp_sin1=27; end
220: begin amp_sin1=29; end
221: begin amp_sin1=31; end
222: begin amp_sin1=33; end
223: begin amp_sin1=35; end
224: begin amp_sin1=37; end
225: begin amp_sin1=40; end
226: begin amp_sin1=42; end
227: begin amp_sin1=44; end
228: begin amp_sin1=47; end
229: begin amp_sin1=49; end
230: begin amp_sin1=52; end
231: begin amp_sin1=54; end
232: begin amp_sin1=57; end
233: begin amp_sin1=60; end
234: begin amp_sin1=62; end
235: begin amp_sin1=65; end
236: begin amp_sin1=68; end
237: begin amp_sin1=70; end
238: begin amp_sin1=73; end
239: begin amp_sin1=76; end
240: begin amp_sin1=79; end
241: begin amp_sin1=82; end
242: begin amp_sin1=85; end
243: begin amp_sin1=88; end
244: begin amp_sin1=91; end
245: begin amp_sin1=94; end
246: begin amp_sin1=97; end
247: begin amp_sin1=100; end
248: begin amp_sin1=103; end
249: begin amp_sin1=106; end
250: begin amp_sin1=109; end
251: begin amp_sin1=112; end
252: begin amp_sin1=115; end
253: begin amp_sin1=119; end
254: begin amp_sin1=122; end
255: begin amp_sin1=125; end
endcase
end
always @(posedge pll_clk) //三角波模块,步长为3，幅值为297,每400个pll_clk为一个周期
if(reset) //复位信号
begin
sign_sanjiao=0;
flag_sanjiao=0;
amp_sanjiao=0;
end
else
begin
if(flag_sanjiao==0)
if(amp_sanjiao==294)
begin
amp_sanjiao=297;
flag_sanjiao=1;
end
else
begin
amp_sanjiao=amp_sanjiao+3;
flag_sanjiao=flag_sanjiao;
end
else if(flag_sanjiao==1)
if(amp_sanjiao==3)
begin
amp_sanjiao=0;
flag_sanjiao=0;
sign_sanjiao=!sign_sanjiao;
end
else
begin
amp_sanjiao=amp_sanjiao-3;
sign_sanjiao=sign_sanjiao;
end
end
/////第一路PWM输出/////////////////////////////////
always @(posedge pll_clk) //pwm定义:当amp_sanjiao>sin_out时为高电平，否则为低电平(注:考虑了符号)
begin
if(flag_sanjiao==0)
begin
if(amp_sanjiao>=amp_sin1)
begin
pwm11=1;
pwm33=0;
end
else
begin
if(flag_sin1==0)
begin
pwm11=0;
pwm33=1;
end
else
begin
pwm11=1;
pwm33=0;
end
end
end
else
begin
if(flag_sin1==0)
begin
pwm11=0;
pwm33=1;
end
else
if(amp_sanjiao<=amp_sin1)
begin
pwm11=1;
pwm33=0;
end
else
begin
pwm11=0;
pwm33=1;
end
end
end
////////////////////////////////////////////////////////
always @(posedge pll_clk)
begin
if(temp_cnt==2)
begin
temp_cnt=0;
pwm1<=pwm11;
pwm3<=pwm33;
pwm2<=pwm11;
pwm4<=pwm33;
end
else
temp_cnt=temp_cnt+1;
end
///////////////////////////////////////////////////////
endmodule⌨️ 快捷键说明
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