double_subc_16bits.v

Verilog 下 16位除法算法程序

module double_subc_16bits( clk,bcs1,cs1,san1,bcs2,cs2,san2);
	input clk;
	input [15:0]bcs1,cs1,bcs2,cs2;
	output [15:0]san1,san2;//,yushu;
	reg [15:0]san1,san2;//,yushu;
	reg [4:0] cnt;
    reg [31:0] a;
	reg [15:0] cs;
    reg [2:0] num;
    always @(posedge clk)
      begin
		   case (cnt)
		        0:
		          begin
						cnt=cnt+1;
						if(num==0)
		                    begin a=bcs1+(cs1>>1);cs=cs1;end
						if(num==1)
							begin a=bcs2;cs=cs2; end
		          end
		       17:
				  begin
						num=num+1;
						cnt=0;
						if(num==1)
						    san1=a[15:0];
						if(num==2)
							san2=a[15:0];
				  end
		        default:
		          begin
		                 if(a>=(cs<<15))
								a=((a-(cs<<15))<<1)+1;
						 else
								a=a<<1;
						 cnt=cnt+1;
		          end
		   endcase
		   
      end
      
endmodule