⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 double_subc_16bits.rpt

📁 Verilog 下 16位除法算法程序
💻 RPT
📖 第 1 页 / 共 5 页
字号:
02:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
03:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
05:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
06:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
07:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
08:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
09:      3/24( 12%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
10:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
11:      5/24( 20%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
12:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
13:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
14:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
17:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
20:      4/24( 16%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      4/24( 16%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      3/24( 12%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      3/24( 12%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
25:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
26:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
27:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
28:      4/24( 16%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
29:      3/24( 12%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
30:      3/24( 12%)     1/4( 25%)      2/4( 50%)       0/4(  0%)
31:      3/24( 12%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
32:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
33:      3/24( 12%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
34:      2/24(  8%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
35:      8/24( 33%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
36:      4/24( 16%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:f:\code\verilog\double_subc\double_subc_16bits.rpt
double_subc_16bits

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       88         clk


Device-Specific Information:f:\code\verilog\double_subc\double_subc_16bits.rpt
double_subc_16bits

** EQUATIONS **

bcs10    : INPUT;
bcs11    : INPUT;
bcs12    : INPUT;
bcs13    : INPUT;
bcs14    : INPUT;
bcs15    : INPUT;
bcs16    : INPUT;
bcs17    : INPUT;
bcs18    : INPUT;
bcs19    : INPUT;
bcs20    : INPUT;
bcs21    : INPUT;
bcs22    : INPUT;
bcs23    : INPUT;
bcs24    : INPUT;
bcs25    : INPUT;
bcs26    : INPUT;
bcs27    : INPUT;
bcs28    : INPUT;
bcs29    : INPUT;
bcs110   : INPUT;
bcs111   : INPUT;
bcs112   : INPUT;
bcs113   : INPUT;
bcs114   : INPUT;
bcs115   : INPUT;
bcs210   : INPUT;
bcs211   : INPUT;
bcs212   : INPUT;
bcs213   : INPUT;
bcs214   : INPUT;
bcs215   : INPUT;
clk      : INPUT;
cs10     : INPUT;
cs11     : INPUT;
cs12     : INPUT;
cs13     : INPUT;
cs14     : INPUT;
cs15     : INPUT;
cs16     : INPUT;
cs17     : INPUT;
cs18     : INPUT;
cs19     : INPUT;
cs20     : INPUT;
cs21     : INPUT;
cs22     : INPUT;
cs23     : INPUT;
cs24     : INPUT;
cs25     : INPUT;
cs26     : INPUT;
cs27     : INPUT;
cs28     : INPUT;
cs29     : INPUT;
cs110    : INPUT;
cs111    : INPUT;
cs112    : INPUT;
cs113    : INPUT;
cs114    : INPUT;
cs115    : INPUT;
cs210    : INPUT;
cs211    : INPUT;
cs212    : INPUT;
cs213    : INPUT;
cs214    : INPUT;
cs215    : INPUT;

-- Node name is ':906' = 'a0' 
-- Equation name is 'a0', location is LC8_B20, type is buried.
a0       = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  _LC4_B20
         #  _LC7_B20
         #  a0 &  _LC1_F28;

-- Node name is ':905' = 'a1' 
-- Equation name is 'a1', location is LC3_D21, type is buried.
a1       = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  _LC6_D21
         #  _LC3_B20
         #  a1 &  _LC1_F28;

-- Node name is ':904' = 'a2' 
-- Equation name is 'a2', location is LC1_D20, type is buried.
a2       = DFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  _LC6_D20
         #  _LC7_D20
         #  a2 &  _LC1_F28;

-- Node name is ':903' = 'a3' 
-- Equation name is 'a3', location is LC1_D32, type is buried.
a3       = DFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  _LC7_D32
         #  _LC8_D32
         #  a3 &  _LC1_F28;

-- Node name is ':902' = 'a4' 
-- Equation name is 'a4', location is LC2_F15, type is buried.
a4       = DFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  _LC4_F15
         #  _LC5_F15
         #  a4 &  _LC1_F28;

-- Node name is ':901' = 'a5' 
-- Equation name is 'a5', location is LC1_F15, type is buried.
a5       = DFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  _LC7_F15
         #  _LC8_F15
         #  a5 &  _LC1_F28;

-- Node name is ':900' = 'a6' 
-- Equation name is 'a6', location is LC2_F10, type is buried.
a6       = DFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  _LC6_F10
         #  _LC7_F10
         #  a6 &  _LC1_F28;

-- Node name is ':899' = 'a7' 
-- Equation name is 'a7', location is LC3_E12, type is buried.
a7       = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  _LC4_E12
         #  _LC5_E12
         #  a7 &  _LC1_F28;

-- Node name is ':898' = 'a8' 
-- Equation name is 'a8', location is LC1_E12, type is buried.
a8       = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  _LC7_E12
         #  _LC8_E12
         #  a8 &  _LC1_F28;

-- Node name is ':897' = 'a9' 
-- Equation name is 'a9', location is LC1_E1, type is buried.
a9       = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  _LC7_E1
         #  _LC8_E1
         #  a9 &  _LC1_F28;

-- Node name is ':896' = 'a10' 
-- Equation name is 'a10', location is LC1_E33, type is buried.
a10      = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 =  _LC5_E33
         #  _LC6_E33
         #  a10 &  _LC1_F28;

-- Node name is ':895' = 'a11' 
-- Equation name is 'a11', location is LC4_E35, type is buried.
a11      = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  _LC6_E35
         #  _LC7_E35
         #  a11 &  _LC1_F28;

-- Node name is ':894' = 'a12' 
-- Equation name is 'a12', location is LC2_E24, type is buried.
a12      = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 =  _LC4_E24
         #  _LC5_E24
         #  a12 &  _LC1_F28;

-- Node name is ':893' = 'a13' 
-- Equation name is 'a13', location is LC1_E24, type is buried.
a13      = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 =  _LC7_E24
         #  _LC8_E24
         #  a13 &  _LC1_F28;

-- Node name is ':892' = 'a14' 
-- Equation name is 'a14', location is LC1_E36, type is buried.
a14      = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 =  _LC7_E36
         #  _LC8_E36
         #  a14 &  _LC1_F28;

-- Node name is ':891' = 'a15' 
-- Equation name is 'a15', location is LC1_D35, type is buried.
a15      = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 =  _LC7_D35
         #  _LC8_D35
         #  a15 &  _LC1_F28;

-- Node name is ':890' = 'a16' 
-- Equation name is 'a16', location is LC4_D35, type is buried.
a16      = DFFE( _EQ017, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ017 =  _LC2_D35
         #  _LC5_D35
         #  a16 &  _LC1_F28;

-- Node name is ':889' = 'a17' 

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -