📄 double_subc_16bits.rpt
字号:
- 5 - E 20 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry22
- 2 - E 34 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry23
- 7 - E 34 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry24
- 4 - E 34 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry25
- 2 - E 25 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry26
- 8 - E 25 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry27
- 5 - E 25 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry28
- 4 - E 29 OR2 0 3 0 1 |lpm_add_sub:1146|addcore:adder|pcarry29
- 2 - F 28 OR2 s ! 0 3 0 2 ~98~1
- 4 - F 28 OR2 ! 0 3 0 52 :98
- 1 - F 28 AND2 0 3 0 70 :109
- 8 - F 28 DFFE + 0 3 0 2 cnt4 (:130)
- 6 - F 28 DFFE + 0 2 0 2 cnt3 (:131)
- 7 - F 28 DFFE + 0 3 0 2 cnt2 (:132)
- 3 - F 28 DFFE + 0 2 0 3 cnt1 (:133)
- 2 - F 32 DFFE + 0 0 0 5 cnt0 (:134)
- 7 - D 36 DFFE + 0 3 0 2 num2 (:145)
- 6 - D 36 DFFE + 0 2 0 3 num1 (:146)
- 4 - D 36 DFFE + 0 1 0 4 num0 (:147)
- 2 - D 36 OR2 ! 0 3 0 51 :155
- 5 - D 36 OR2 ! 0 3 0 51 :176
- 3 - D 35 OR2 1 3 0 1 :245
- 6 - D 35 OR2 1 3 0 1 :246
- 6 - E 36 OR2 0 3 0 1 :247
- 6 - E 24 OR2 0 3 0 1 :248
- 3 - E 24 OR2 0 3 0 1 :249
- 5 - E 35 OR2 0 3 0 1 :250
- 4 - E 33 OR2 0 3 0 1 :251
- 6 - E 01 OR2 0 3 0 1 :252
- 6 - E 12 OR2 0 3 0 1 :253
- 2 - E 12 OR2 0 3 0 1 :254
- 5 - F 10 OR2 0 3 0 1 :255
- 6 - F 15 OR2 0 3 0 1 :256
- 3 - F 15 OR2 0 3 0 1 :257
- 6 - D 32 OR2 0 3 0 1 :258
- 5 - D 20 OR2 0 3 0 1 :259
- 5 - D 21 OR2 1 3 0 1 :260
- 5 - B 20 OR2 2 2 0 1 :261
- 5 - D 35 AND2 0 3 0 1 :341
- 7 - D 35 OR2 1 3 0 1 :342
- 7 - E 36 OR2 1 3 0 1 :343
- 7 - E 24 OR2 1 3 0 1 :344
- 4 - E 24 OR2 1 3 0 1 :345
- 6 - E 35 OR2 1 3 0 1 :346
- 5 - E 33 OR2 1 3 0 1 :347
- 7 - E 01 OR2 1 3 0 1 :348
- 7 - E 12 OR2 1 3 0 1 :349
- 4 - E 12 OR2 1 3 0 1 :350
- 6 - F 10 OR2 1 3 0 1 :351
- 7 - F 15 OR2 1 3 0 1 :352
- 4 - F 15 OR2 1 3 0 1 :353
- 7 - D 32 OR2 1 3 0 1 :354
- 6 - D 20 OR2 1 3 0 1 :355
- 6 - D 21 OR2 1 3 0 1 :356
- 7 - B 20 OR2 1 3 0 1 :357
- 2 - D 21 AND2 ! 0 2 0 20 :390
- 7 - E 30 OR2 s 2 2 0 1 ~523~1
- 5 - E 30 OR2 s 2 2 0 1 ~524~1
- 8 - E 22 OR2 s 2 2 0 1 ~525~1
- 7 - E 22 OR2 s 2 2 0 1 ~526~1
- 6 - E 22 OR2 s 2 2 0 1 ~527~1
- 8 - E 03 OR2 s 2 2 0 1 ~528~1
- 2 - E 03 OR2 s 2 2 0 1 ~529~1
- 1 - E 03 OR2 s 2 2 0 1 ~530~1
- 8 - F 36 OR2 s 2 2 0 1 ~531~1
- 6 - F 36 OR2 s 2 2 0 1 ~532~1
- 5 - F 36 OR2 s 2 2 0 1 ~533~1
- 4 - D 32 OR2 s 2 2 0 1 ~534~1
- 3 - D 36 OR2 s 2 2 0 1 ~535~1
- 4 - D 21 OR2 s 2 2 0 1 ~536~1
- 4 - D 24 OR2 s 2 2 0 1 ~537~1
- 1 - B 20 OR2 s 0 3 0 16 ~538~1
- 8 - D 24 OR2 s 2 2 0 1 ~538~2
- 3 - E 30 DFFE + 0 3 0 2 :539
- 2 - E 30 DFFE + 0 3 0 3 :540
- 3 - E 22 DFFE + 0 3 0 3 :541
- 1 - E 22 DFFE + 0 3 0 3 :542
- 2 - E 22 DFFE + 0 3 0 3 :543
- 5 - E 03 DFFE + 0 3 0 3 :544
- 4 - E 03 DFFE + 0 3 0 3 cs9 (:545)
- 6 - E 03 DFFE + 0 3 0 3 cs8 (:546)
- 2 - F 36 DFFE + 0 3 0 3 cs7 (:547)
- 4 - F 36 DFFE + 0 3 0 3 cs6 (:548)
- 1 - F 36 DFFE + 0 3 0 3 cs5 (:549)
- 2 - D 32 DFFE + 0 3 0 3 cs4 (:550)
- 8 - D 36 DFFE + 0 3 0 3 cs3 (:551)
- 8 - D 21 DFFE + 0 3 0 3 cs2 (:552)
- 5 - D 24 DFFE + 0 3 0 3 cs1 (:553)
- 2 - D 24 DFFE + 0 3 0 4 cs0 (:554)
- 2 - E 29 OR2 0 4 0 17 :557
- 1 - E 29 OR2 0 3 0 1 :565
- 2 - E 19 OR2 0 3 0 1 :570
- 8 - E 19 OR2 0 3 0 1 :575
- 7 - E 19 OR2 0 3 0 1 :580
- 6 - E 19 OR2 0 3 0 1 :585
- 5 - E 19 OR2 0 3 0 1 :590
- 4 - E 19 OR2 0 3 0 1 :595
- 3 - E 19 OR2 0 3 0 1 :600
- 1 - E 19 OR2 0 3 0 1 :605
- 1 - D 24 OR2 0 3 0 1 :610
- 7 - D 24 OR2 0 3 0 1 :615
- 6 - D 24 OR2 0 3 0 1 :620
- 1 - D 33 OR2 0 3 0 1 :625
- 2 - D 33 OR2 0 4 0 1 :630
- 5 - E 29 OR2 0 4 0 1 :779
- 7 - E 29 OR2 0 4 0 1 :780
- 4 - E 25 OR2 0 4 0 1 :781
- 7 - E 25 OR2 0 4 0 1 :782
- 1 - E 25 OR2 0 4 0 1 :783
- 8 - E 34 OR2 0 4 0 1 :784
- 6 - E 34 OR2 0 4 0 1 :785
- 4 - E 20 OR2 0 4 0 1 :786
- 8 - E 20 OR2 0 4 0 1 :787
- 1 - E 20 OR2 0 4 0 1 :788
- 2 - D 23 OR2 0 4 0 1 :789
- 4 - D 23 OR2 0 4 0 1 :790
- 1 - D 23 OR2 0 4 0 1 :791
- 8 - D 33 OR2 0 4 0 1 :792
- 3 - D 33 OR2 0 4 0 1 :793
- 2 - D 35 OR2 0 4 0 1 :826
- 8 - D 35 AND2 0 3 0 1 :827
- 8 - E 36 AND2 0 3 0 1 :828
- 8 - E 24 AND2 0 3 0 1 :829
- 5 - E 24 AND2 0 3 0 1 :830
- 7 - E 35 AND2 0 3 0 1 :831
- 6 - E 33 AND2 0 3 0 1 :832
- 8 - E 01 AND2 0 3 0 1 :833
- 8 - E 12 AND2 0 3 0 1 :834
- 5 - E 12 AND2 0 3 0 1 :835
- 7 - F 10 AND2 0 3 0 1 :836
- 8 - F 15 AND2 0 3 0 1 :837
- 5 - F 15 AND2 0 3 0 1 :838
- 8 - D 32 AND2 0 3 0 1 :839
- 7 - D 20 AND2 0 3 0 1 :840
- 3 - B 20 AND2 0 3 0 1 :841
- 4 - B 20 AND2 0 3 0 1 :842
- 1 - D 21 OR2 s 0 4 0 15 ~857~1
- 6 - E 29 DFFE + 0 3 0 1 a31 (:875)
- 8 - E 29 DFFE + 0 3 0 2 a30 (:876)
- 3 - E 29 DFFE + 0 3 0 3 a29 (:877)
- 6 - E 25 DFFE + 0 3 0 3 a28 (:878)
- 3 - E 25 DFFE + 0 3 0 3 a27 (:879)
- 3 - E 34 DFFE + 0 3 0 3 a26 (:880)
- 5 - E 34 DFFE + 0 3 0 3 a25 (:881)
- 1 - E 34 DFFE + 0 3 0 3 a24 (:882)
- 2 - E 20 DFFE + 0 3 0 3 a23 (:883)
- 6 - E 20 DFFE + 0 3 0 3 a22 (:884)
- 3 - E 20 DFFE + 0 3 0 3 a21 (:885)
- 6 - D 23 DFFE + 0 3 0 3 a20 (:886)
- 7 - D 23 DFFE + 0 3 0 3 a19 (:887)
- 6 - D 33 DFFE + 0 3 0 3 a18 (:888)
- 5 - D 33 DFFE + 0 3 0 3 a17 (:889)
- 4 - D 35 DFFE + 0 3 0 4 a16 (:890)
- 1 - D 35 DFFE + 0 3 0 7 a15 (:891)
- 1 - E 36 DFFE + 0 3 0 4 a14 (:892)
- 1 - E 24 DFFE + 0 3 0 4 a13 (:893)
- 2 - E 24 DFFE + 0 3 0 4 a12 (:894)
- 4 - E 35 DFFE + 0 3 0 4 a11 (:895)
- 1 - E 33 DFFE + 0 3 0 4 a10 (:896)
- 1 - E 01 DFFE + 0 3 0 4 a9 (:897)
- 1 - E 12 DFFE + 0 3 0 4 a8 (:898)
- 3 - E 12 DFFE + 0 3 0 4 a7 (:899)
- 2 - F 10 DFFE + 0 3 0 4 a6 (:900)
- 1 - F 15 DFFE + 0 3 0 4 a5 (:901)
- 2 - F 15 DFFE + 0 3 0 4 a4 (:902)
- 1 - D 32 DFFE + 0 3 0 4 a3 (:903)
- 1 - D 20 DFFE + 0 3 0 4 a2 (:904)
- 3 - D 21 DFFE + 0 3 0 4 a1 (:905)
- 8 - B 20 DFFE + 0 3 0 4 a0 (:906)
- 7 - F 01 DFFE + 0 3 1 0 :1005
- 4 - C 33 DFFE + 0 3 1 0 :1006
- 1 - C 33 DFFE + 0 3 1 0 :1007
- 7 - E 11 DFFE + 0 3 1 0 :1008
- 6 - E 11 DFFE + 0 3 1 0 :1009
- 2 - E 33 DFFE + 0 3 1 0 :1010
- 8 - E 33 DFFE + 0 3 1 0 :1011
- 5 - E 11 DFFE + 0 3 1 0 :1012
- 3 - E 11 DFFE + 0 3 1 0 :1013
- 5 - F 01 DFFE + 0 3 1 0 :1014
- 3 - F 01 DFFE + 0 3 1 0 :1015
- 4 - F 01 DFFE + 0 3 1 0 :1016
- 4 - E 30 DFFE + 0 3 1 0 :1017
- 8 - E 30 DFFE + 0 3 1 0 :1018
- 6 - E 30 DFFE + 0 3 1 0 :1019
- 6 - B 20 DFFE + 0 3 1 0 :1020
- 6 - F 01 DFFE + 0 3 1 0 :1126
- 2 - C 33 DFFE + 0 3 1 0 :1127
- 7 - C 33 DFFE + 0 3 1 0 :1128
- 8 - E 11 DFFE + 0 3 1 0 :1129
- 2 - E 11 DFFE + 0 3 1 0 :1130
- 3 - E 33 DFFE + 0 3 1 0 :1131
- 7 - E 33 DFFE + 0 3 1 0 :1132
- 4 - E 11 DFFE + 0 3 1 0 :1133
- 1 - E 11 DFFE + 0 3 1 0 :1134
- 8 - F 01 DFFE + 0 3 1 0 :1135
- 1 - F 01 DFFE + 0 3 1 0 :1136
- 2 - F 01 DFFE + 0 3 1 0 :1137
- 1 - E 30 DFFE + 0 3 1 0 :1138
- 6 - C 33 DFFE + 0 3 1 0 :1139
- 1 - D 36 DFFE + 0 3 1 0 :1140
- 2 - B 20 DFFE + 0 3 1 0 :1141
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:f:\code\verilog\double_subc\double_subc_16bits.rpt
double_subc_16bits
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/144( 1%) 2/ 72( 2%) 1/ 72( 1%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 6/144( 4%) 0/ 72( 0%) 3/ 72( 4%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
C: 7/144( 4%) 1/ 72( 1%) 5/ 72( 6%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
D: 36/144( 25%) 0/ 72( 0%) 12/ 72( 16%) 10/16( 62%) 0/16( 0%) 0/16( 0%)
E: 54/144( 37%) 14/ 72( 19%) 25/ 72( 34%) 2/16( 12%) 5/16( 31%) 0/16( 0%)
F: 18/144( 12%) 10/ 72( 13%) 3/ 72( 4%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
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