📄 double_subc_16bits.rpt
字号:
F36 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 91/96 ( 94%)
Total logic cells used: 237/1728 ( 13%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.56/4 ( 89%)
Total fan-in: 846/6912 ( 12%)
Total input pins required: 65
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 237
Total flipflops required: 88
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 20/1728 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 5/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 0 8 8 0 0 0 0 0 0 0 8 8 0 8 8 63/0
E: 8 0 8 0 0 0 0 0 0 0 8 8 0 0 0 0 0 0 0 8 8 0 8 0 8 8 0 0 0 8 8 0 0 8 8 8 8 120/0
F: 8 0 0 0 0 0 0 0 0 8 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 1 0 0 0 8 41/0
Total: 16 0 8 0 0 0 0 0 0 8 8 8 0 0 8 0 0 0 0 8 24 7 8 8 16 8 0 0 8 8 8 0 9 21 8 16 24 237/0
Device-Specific Information:f:\code\verilog\double_subc\double_subc_16bits.rpt
double_subc_16bits
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
144 - - - 36 INPUT ^ 0 0 0 3 bcs10
135 - - - 29 INPUT ^ 0 0 0 2 bcs11
113 - - - 05 INPUT ^ 0 0 0 2 bcs12
49 - - - 21 INPUT ^ 0 0 0 2 bcs13
42 - - - 28 INPUT ^ 0 0 0 2 bcs14
117 - - - 08 INPUT ^ 0 0 0 2 bcs15
73 - - - 01 INPUT ^ 0 0 0 2 bcs16
112 - - - 04 INPUT ^ 0 0 0 2 bcs17
119 - - - 13 INPUT ^ 0 0 0 2 bcs18
116 - - - 07 INPUT ^ 0 0 0 2 bcs19
98 - - B -- INPUT ^ 0 0 0 1 bcs20
89 - - D -- INPUT ^ 0 0 0 1 bcs21
19 - - D -- INPUT ^ 0 0 0 1 bcs22
88 - - D -- INPUT ^ 0 0 0 1 bcs23
67 - - - 08 INPUT ^ 0 0 0 1 bcs24
64 - - - 10 INPUT ^ 0 0 0 1 bcs25
68 - - - 07 INPUT ^ 0 0 0 1 bcs26
120 - - - 14 INPUT ^ 0 0 0 1 bcs27
118 - - - 09 INPUT ^ 0 0 0 1 bcs28
111 - - - 03 INPUT ^ 0 0 0 1 bcs29
143 - - - 35 INPUT ^ 0 0 0 2 bcs110
72 - - - 03 INPUT ^ 0 0 0 2 bcs111
51 - - - 20 INPUT ^ 0 0 0 2 bcs112
133 - - - 28 INPUT ^ 0 0 0 2 bcs113
87 - - E -- INPUT ^ 0 0 0 2 bcs114
20 - - D -- INPUT ^ 0 0 0 2 bcs115
132 - - - 26 INPUT ^ 0 0 0 1 bcs210
36 - - - 36 INPUT ^ 0 0 0 1 bcs211
39 - - - 33 INPUT ^ 0 0 0 1 bcs212
46 - - - 27 INPUT ^ 0 0 0 1 bcs213
47 - - - 25 INPUT ^ 0 0 0 1 bcs214
91 - - D -- INPUT ^ 0 0 0 1 bcs215
55 - - - -- INPUT G ^ 0 0 0 0 clk
141 - - - 33 INPUT ^ 0 0 0 1 cs10
54 - - - -- INPUT ^ 0 0 0 4 cs11
92 - - D -- INPUT ^ 0 0 0 3 cs12
56 - - - -- INPUT ^ 0 0 0 3 cs13
21 - - D -- INPUT ^ 0 0 0 3 cs14
80 - - F -- INPUT ^ 0 0 0 3 cs15
124 - - - -- INPUT ^ 0 0 0 3 cs16
126 - - - -- INPUT ^ 0 0 0 3 cs17
59 - - - 16 INPUT ^ 0 0 0 3 cs18
125 - - - -- INPUT ^ 0 0 0 3 cs19
23 - - D -- INPUT ^ 0 0 0 1 cs20
22 - - D -- INPUT ^ 0 0 0 1 cs21
136 - - - 30 INPUT ^ 0 0 0 1 cs22
90 - - D -- INPUT ^ 0 0 0 1 cs23
38 - - - 34 INPUT ^ 0 0 0 1 cs24
32 - - F -- INPUT ^ 0 0 0 1 cs25
30 - - F -- INPUT ^ 0 0 0 1 cs26
31 - - F -- INPUT ^ 0 0 0 1 cs27
114 - - - 06 INPUT ^ 0 0 0 1 cs28
121 - - - 17 INPUT ^ 0 0 0 1 cs29
102 - - A -- INPUT ^ 0 0 0 3 cs110
28 - - E -- INPUT ^ 0 0 0 3 cs111
130 - - - 22 INPUT ^ 0 0 0 3 cs112
131 - - - 23 INPUT ^ 0 0 0 3 cs113
48 - - - 24 INPUT ^ 0 0 0 3 cs114
41 - - - 31 INPUT ^ 0 0 0 3 cs115
70 - - - 05 INPUT ^ 0 0 0 1 cs210
140 - - - 32 INPUT ^ 0 0 0 1 cs211
128 - - - 19 INPUT ^ 0 0 0 1 cs212
138 - - - 31 INPUT ^ 0 0 0 1 cs213
69 - - - 06 INPUT ^ 0 0 0 1 cs214
65 - - - 09 INPUT ^ 0 0 0 1 cs215
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:f:\code\verilog\double_subc\double_subc_16bits.rpt
double_subc_16bits
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
10 - - B -- OUTPUT 0 1 0 0 san10
137 - - - 30 OUTPUT 0 1 0 0 san11
44 - - - 29 OUTPUT 0 1 0 0 san12
43 - - - 30 OUTPUT 0 1 0 0 san13
96 - - C -- OUTPUT 0 1 0 0 san14
109 - - - 01 OUTPUT 0 1 0 0 san15
110 - - - 02 OUTPUT 0 1 0 0 san16
13 - - C -- OUTPUT 0 1 0 0 san17
7 - - A -- OUTPUT 0 1 0 0 san18
83 - - E -- OUTPUT 0 1 0 0 san19
9 - - B -- OUTPUT 0 1 0 0 san20
37 - - - 35 OUTPUT 0 1 0 0 san21
17 - - C -- OUTPUT 0 1 0 0 san22
26 - - E -- OUTPUT 0 1 0 0 san23
81 - - F -- OUTPUT 0 1 0 0 san24
82 - - F -- OUTPUT 0 1 0 0 san25
78 - - F -- OUTPUT 0 1 0 0 san26
63 - - - 11 OUTPUT 0 1 0 0 san27
86 - - E -- OUTPUT 0 1 0 0 san28
8 - - A -- OUTPUT 0 1 0 0 san29
142 - - - 34 OUTPUT 0 1 0 0 san110
79 - - F -- OUTPUT 0 1 0 0 san111
33 - - F -- OUTPUT 0 1 0 0 san112
11 - - C -- OUTPUT 0 1 0 0 san113
14 - - C -- OUTPUT 0 1 0 0 san114
29 - - E -- OUTPUT 0 1 0 0 san115
27 - - E -- OUTPUT 0 1 0 0 san210
62 - - - 12 OUTPUT 0 1 0 0 san211
100 - - A -- OUTPUT 0 1 0 0 san212
18 - - C -- OUTPUT 0 1 0 0 san213
12 - - C -- OUTPUT 0 1 0 0 san214
101 - - A -- OUTPUT 0 1 0 0 san215
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:f:\code\verilog\double_subc\double_subc_16bits.rpt
double_subc_16bits
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - F 28 AND2 0 3 0 2 |lpm_add_sub:1143|addcore:adder|:63
- 3 - D 20 OR2 4 0 0 2 |lpm_add_sub:1145|addcore:adder|pcarry1
- 2 - D 20 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry2
- 3 - D 32 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry3
- 7 - F 36 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry4
- 3 - F 10 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry5
- 1 - F 10 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry6
- 7 - E 03 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry7
- 4 - E 01 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry8
- 3 - E 01 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry9
- 1 - E 35 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry10
- 3 - E 35 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry11
- 5 - E 22 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry12
- 3 - E 36 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry13
- 2 - E 36 OR2 2 1 0 2 |lpm_add_sub:1145|addcore:adder|pcarry14
- 8 - D 20 OR2 s 3 0 0 1 |lpm_add_sub:1145|addcore:adder|~178~1
- 4 - D 20 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:179
- 5 - D 32 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:180
- 3 - F 36 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:181
- 8 - F 10 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:182
- 4 - F 10 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:183
- 3 - E 03 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:184
- 2 - E 01 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:185
- 5 - E 01 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:186
- 8 - E 35 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:187
- 2 - E 35 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:188
- 4 - E 22 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:189
- 4 - E 36 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:190
- 5 - E 36 OR2 2 1 0 1 |lpm_add_sub:1145|addcore:adder|:191
- 3 - D 24 OR2 0 2 0 1 |lpm_add_sub:1146|addcore:adder|pcarry15
- 7 - D 33 OR2 0 4 0 2 |lpm_add_sub:1146|addcore:adder|pcarry16
- 4 - D 33 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry17
- 3 - D 23 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry18
- 5 - D 23 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry19
- 8 - D 23 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry20
- 7 - E 20 OR2 0 3 0 2 |lpm_add_sub:1146|addcore:adder|pcarry21
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