📄 double_subc_16bits.rpt
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Project Information f:\code\verilog\double_subc\double_subc_16bits.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 09/22/2006 22:07:28
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
double_subc_16bits
EPF10K30ETC144-1 65 32 0 0 0 % 237 13 %
User Pins: 65 32 0
Project Information f:\code\verilog\double_subc\double_subc_16bits.rpt
** PROJECT COMPILATION MESSAGES **
Info: Design Doctor has given the project a clean bill of health based on the EPLD Rules set
Project Information f:\code\verilog\double_subc\double_subc_16bits.rpt
** FILE HIERARCHY **
|lpm_add_sub:1142|
|lpm_add_sub:1142|addcore:adder|
|lpm_add_sub:1142|altshift:result_ext_latency_ffs|
|lpm_add_sub:1142|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1142|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1143|
|lpm_add_sub:1143|addcore:adder|
|lpm_add_sub:1143|altshift:result_ext_latency_ffs|
|lpm_add_sub:1143|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1143|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1144|
|lpm_add_sub:1144|addcore:adder|
|lpm_add_sub:1144|altshift:result_ext_latency_ffs|
|lpm_add_sub:1144|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1144|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1145|
|lpm_add_sub:1145|addcore:adder|
|lpm_add_sub:1145|altshift:result_ext_latency_ffs|
|lpm_add_sub:1145|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1145|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1146|
|lpm_add_sub:1146|addcore:adder|
|lpm_add_sub:1146|altshift:result_ext_latency_ffs|
|lpm_add_sub:1146|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1146|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1147|
|lpm_add_sub:1147|addcore:adder|
|lpm_add_sub:1147|altshift:result_ext_latency_ffs|
|lpm_add_sub:1147|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1147|altshift:oflow_ext_latency_ffs|
Device-Specific Information:f:\code\verilog\double_subc\double_subc_16bits.rpt
double_subc_16bits
***** Logic for device 'double_subc_16bits' compiled without errors.
Device: EPF10K30ETC144-1
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Device-Specific Information:f:\code\verilog\double_subc\double_subc_16bits.rpt
double_subc_16bits
** ERROR SUMMARY **
Info: Chip 'double_subc_16bits' in device 'EPF10K30ETC144-1' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R
E
b s b b V S
b c a c c s b V c c c c c C E b b b b b V b b b s s
c s n c s s a c c C s s s s s c c c C R c c c c c c C c c c c a a
s 1 1 s 2 G 2 n s s C 1 2 1 1 G 2 G s s s I V s s s s s s C s s s s n n
1 1 1 1 1 N 1 1 2 1 I 1 1 1 1 N 1 N 1 1 1 N E 2 2 1 2 1 1 I 2 1 1 2 1 1
0 0 0 0 1 D 3 1 2 1 O 3 0 3 2 D 2 D 7 9 6 T D 9 7 8 8 5 9 O 8 2 7 9 6 5
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
VCCINT | 6 103 | GND
san18 | 7 102 | cs110
san29 | 8 101 | san215
san20 | 9 100 | san212
san10 | 10 99 | RESERVED
san113 | 11 98 | bcs20
san214 | 12 97 | RESERVED
san17 | 13 96 | san14
san114 | 14 95 | RESERVED
GND | 15 94 | VCCIO
GND | 16 93 | VCCINT
san22 | 17 92 | cs12
san213 | 18 91 | bcs215
bcs22 | 19 EPF10K30ETC144-1 90 | cs23
bcs115 | 20 89 | bcs21
cs14 | 21 88 | bcs23
cs21 | 22 87 | bcs114
cs20 | 23 86 | san28
VCCIO | 24 85 | GND
VCCINT | 25 84 | GND
san23 | 26 83 | san19
san210 | 27 82 | san25
cs111 | 28 81 | san24
san115 | 29 80 | cs15
cs26 | 30 79 | san111
cs27 | 31 78 | san26
cs25 | 32 77 | ^MSEL0
san112 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
bcs211 | 36 73 | bcs16
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
s c b G c b s s V b b c b G b V V c c c G G c R V s s b c G b b c c V b
a s c N s c a a C c c s c N c C C s l s N N s E C a a c s N c c s s C c
n 2 s D 1 s n n C s s 1 s D s C C 1 k 1 D D 1 S C n n s 2 D s s 2 2 C s
2 4 2 1 1 1 1 I 2 2 1 1 1 I I 1 3 8 E I 2 2 2 1 2 2 1 1 I 1
1 1 5 4 3 2 O 1 1 4 3 1 N N R O 1 7 5 5 4 6 4 0 O 1
2 3 4 2 T T V 1 1
E
D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information:f:\code\verilog\double_subc\double_subc_16bits.rpt
double_subc_16bits
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B20 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
C33 5/ 8( 62%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
D20 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
D21 7/ 8( 87%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
D23 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
D24 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 16/22( 72%)
D32 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
D33 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
D35 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
D36 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
E1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
E3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
E11 8/ 8(100%) 7/ 8( 87%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
E12 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
E19 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
E20 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
E22 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
E24 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
E25 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
E29 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
E30 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
E33 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
E34 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
E35 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
E36 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
F1 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
F10 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
F15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
F28 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
F32 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
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