segment7.hier_info

7段数码管译码器,用VHDL在FPGA2000上显示

|segment7
clk => count[23].CLK
clk => count[22].CLK
clk => count[21].CLK
clk => count[20].CLK
clk => count[19].CLK
clk => count[18].CLK
clk => count[17].CLK
clk => count[16].CLK
clk => count[15].CLK
clk => count[14].CLK
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => count[24].CLK
sw17 => TEMP~0.OUTPUTSELECT
sw17 => TEMP~1.OUTPUTSELECT
sw17 => TEMP~2.OUTPUTSELECT
sw17 => TEMP~3.OUTPUTSELECT
sw17 => TEMP~8.OUTPUTSELECT
sw17 => TEMP~9.OUTPUTSELECT
sw17 => TEMP~10.OUTPUTSELECT
sw17 => TEMP~11.OUTPUTSELECT
sw17 => led17.DATAIN
sw17 => TEMP~12.OUTPUTSELECT
sw17 => TEMP~13.OUTPUTSELECT
sw17 => TEMP~14.OUTPUTSELECT
sw17 => TEMP~15.OUTPUTSELECT
sw17 => TEMP~4.OUTPUTSELECT
sw17 => TEMP~5.OUTPUTSELECT
sw17 => TEMP~6.OUTPUTSELECT
sw17 => TEMP~7.OUTPUTSELECT
sw[0] => ~NO_FANOUT~
sw[1] => ~NO_FANOUT~
sw[2] => ~NO_FANOUT~
sw[3] => ~NO_FANOUT~
key3 => comb~1.IN0
key3 => comb~2.IN0
key3 => comb~3.IN0
key3 => comb~0.IN0
key3 => comb~4.IN0
key3 => comb~5.IN0
key3 => comb~6.IN0
key3 => comb~7.IN0
key3 => TEMP[3].ENA
key3 => TEMP[2].ENA
key3 => TEMP[1].ENA
key3 => TEMP[0].ENA
hex0[0] <= Mux~10.DB_MAX_OUTPUT_PORT_TYPE
hex0[1] <= Mux~9.DB_MAX_OUTPUT_PORT_TYPE
hex0[2] <= Mux~8.DB_MAX_OUTPUT_PORT_TYPE
hex0[3] <= Mux~7.DB_MAX_OUTPUT_PORT_TYPE
hex0[4] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
hex0[5] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
hex0[6] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
hex1[0] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
hex1[1] <= <GND>
hex1[2] <= <GND>
hex1[3] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
hex1[4] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
hex1[5] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
hex1[6] <= <VCC>
led17 <= sw17.DB_MAX_OUTPUT_PORT_TYPE