segment7.map.qmsg

7段数码管译码器,用VHDL在FPGA2000上显示

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Web Edition " "Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 28 15:53:46 2007 " "Info: Processing started: Wed Nov 28 15:53:46 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off segment7 -c segment7 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off segment7 -c segment7" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "segment7.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file segment7.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 segment7-divide " "Info: Found design unit 1: segment7-divide" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 segment7 " "Info: Found entity 1: segment7" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "segment7 " "Info: Elaborating entity \"segment7\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "segment7.vhd(104) " "Info: VHDL Case Statement information at segment7.vhd(104): OTHERS choice is never selected" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 104 0 0 } }  } 0}
{ "Info" "IOPT_MLS_CREATED_ALOAD_CCT" "" "Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state." {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } } { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 34 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "hex1\[1\] GND " "Warning: Pin \"hex1\[1\]\" stuck at GND" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "hex1\[2\] GND " "Warning: Pin \"hex1\[2\]\" stuck at GND" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "hex1\[6\] VCC " "Warning: Pin \"hex1\[6\]\" stuck at VCC" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 13 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "4 " "Warning: Design contains 4 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "sw\[0\] " "Warning: No output dependent on input pin \"sw\[0\]\"" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 10 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "sw\[1\] " "Warning: No output dependent on input pin \"sw\[1\]\"" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 10 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "sw\[2\] " "Warning: No output dependent on input pin \"sw\[2\]\"" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 10 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "sw\[3\] " "Warning: No output dependent on input pin \"sw\[3\]\"" {  } { { "segment7.vhd" "" { Text "C:/Documents and Settings/student/桌面/evelyn/ex (4)/segment7.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "98 " "Info: Implemented 98 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "76 " "Info: Implemented 76 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 28 15:53:49 2007 " "Info: Processing ended: Wed Nov 28 15:53:49 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}