segment7.fit.summary

来自「7段数码管译码器,用VHDL在FPGA2000上显示」· SUMMARY 代码 · 共 16 行

Flow Status : Successful - Wed Nov 28 15:54:04 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Web Edition
Revision Name : segment7
Top-level Entity Name : segment7
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Preliminary
Met timing requirements : N/A
Total logic elements : 47 / 33,216 ( < 1 % )
Total registers : 29
Total pins : 22 / 475 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )