segment7.tan.summary

7段数码管译码器,用VHDL在FPGA2000上显示

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.061 ns
From           : sw17
To             : TEMP[2]~278
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.008 ns
From           : TEMP[2]~278
To             : hex1[0]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 13.786 ns
From           : sw17
To             : hex1[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.814 ns
From           : key3
To             : TEMP[3]~280
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 339.10 MHz ( period = 2.949 ns )
From           : TEMP[2]~278
To             : TEMP[3]~280
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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