segment7.flow.rpt

来自「7段数码管译码器,用VHDL在FPGA2000上显示」· RPT 代码 · 共 91 行

Flow report for segment7
Wed Nov 28 15:54:17 2007
Version 5.0 Build 148 04/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Flow Summary                                                                 ;
+------------------------------------+-----------------------------------------+
; Flow Status                        ; Successful - Wed Nov 28 15:54:17 2007   ;
; Quartus II Version                 ; 5.0 Build 148 04/26/2005 SJ Web Edition ;
; Revision Name                      ; segment7                                ;
; Top-level Entity Name              ; segment7                                ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C35F672C6                            ;
; Timing Models                      ; Preliminary                             ;
; Met timing requirements            ; Yes                                     ;
; Total logic elements               ; 47 / 33,216 ( < 1 % )                   ;
; Total registers                    ; 29                                      ;
; Total pins                         ; 22 / 475 ( 4 % )                        ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 0 / 483,840 ( 0 % )                     ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                          ;
; Total PLLs                         ; 0 / 4 ( 0 % )                           ;
+------------------------------------+-----------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 11/28/2007 15:53:46 ;
; Main task         ; Compilation         ;
; Revision Name     ; segment7            ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:04     ;
; Fitter               ; 00:00:14     ;
; Assembler            ; 00:00:10     ;
; Timing Analyzer      ; 00:00:02     ;
; Total                ; 00:00:30     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off segment7 -c segment7
quartus_fit --read_settings_files=off --write_settings_files=off segment7 -c segment7
quartus_asm --read_settings_files=off --write_settings_files=off segment7 -c segment7
quartus_tan --read_settings_files=off --write_settings_files=off segment7 -c segment7 --timing_analysis_only