📄 stmch1.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register state.s0 state.s1 464.04 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 464.04 MHz between source register \"state.s0\" and destination register \"state.s1\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.155 ns " "Info: fmax restricted to clock pin edge rate 2.155 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.847 ns + Longest register register " "Info: + Longest register to register delay is 0.847 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.s0 1 REG LCFF_X3_Y35_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { state.s0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.447 ns) 0.761 ns Select~14 2 COMB LCCOMB_X3_Y35_N0 2 " "Info: 2: + IC(0.314 ns) + CELL(0.447 ns) = 0.761 ns; Loc. = LCCOMB_X3_Y35_N0; Fanout = 2; COMB Node = 'Select~14'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.761 ns" { state.s0 Select~14 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 0.847 ns state.s1 3 REG LCFF_X3_Y35_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 0.847 ns; Loc. = LCFF_X3_Y35_N1; Fanout = 2; REG Node = 'state.s1'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.086 ns" { Select~14 state.s1 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.533 ns 62.93 % " "Info: Total cell delay = 0.533 ns ( 62.93 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.314 ns 37.07 % " "Info: Total interconnect delay = 0.314 ns ( 37.07 % )" { } { } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.847 ns" { state.s0 Select~14 state.s1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "0.847 ns" { state.s0 Select~14 state.s1 } { 0.000ns 0.314ns 0.000ns } { 0.000ns 0.447ns 0.086ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.656 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.656 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_A13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_A13; Fanout = 1; CLK Node = 'clk'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { clk } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.058 ns clk~clkctrl 2 COMB CLKCTRL_G10 2 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.058 ns; Loc. = CLKCTRL_G10; Fanout = 2; COMB Node = 'clk~clkctrl'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.113 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.548 ns) 2.656 ns state.s1 3 REG LCFF_X3_Y35_N1 2 " "Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.656 ns; Loc. = LCFF_X3_Y35_N1; Fanout = 2; REG Node = 'state.s1'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "1.598 ns" { clk~clkctrl state.s1 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 56.21 % " "Info: Total cell delay = 1.493 ns ( 56.21 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.163 ns 43.79 % " "Info: Total interconnect delay = 1.163 ns ( 43.79 % )" { } { } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s1 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.656 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.656 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_A13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_A13; Fanout = 1; CLK Node = 'clk'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { clk } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.058 ns clk~clkctrl 2 COMB CLKCTRL_G10 2 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.058 ns; Loc. = CLKCTRL_G10; Fanout = 2; COMB Node = 'clk~clkctrl'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.113 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.548 ns) 2.656 ns state.s0 3 REG LCFF_X3_Y35_N7 1 " "Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.656 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "1.598 ns" { clk~clkctrl state.s0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 56.21 % " "Info: Total cell delay = 1.493 ns ( 56.21 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.163 ns 43.79 % " "Info: Total interconnect delay = 1.163 ns ( 43.79 % )" { } { } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s0 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s1 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s0 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns + " "Info: + Micro clock to output delay of source is 0.255 ns" { } { } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.847 ns" { state.s0 Select~14 state.s1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "0.847 ns" { state.s0 Select~14 state.s1 } { 0.000ns 0.314ns 0.000ns } { 0.000ns 0.447ns 0.086ns } } } { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s1 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s0 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { state.s1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { state.s1 } { } { } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "state.s0 in1 clk 3.546 ns register " "Info: tsu for register \"state.s0\" (data pin = \"in1\", clock pin = \"clk\") is 3.546 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.238 ns + Longest pin register " "Info: + Longest pin to register delay is 6.238 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.804 ns) 0.804 ns in1 1 PIN PIN_A4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.804 ns) = 0.804 ns; Loc. = PIN_A4; Fanout = 2; PIN Node = 'in1'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { in1 } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.761 ns) + CELL(0.673 ns) 6.238 ns state.s0 2 REG LCFF_X3_Y35_N7 1 " "Info: 2: + IC(4.761 ns) + CELL(0.673 ns) = 6.238 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "5.434 ns" { in1 state.s0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.477 ns 23.68 % " "Info: Total cell delay = 1.477 ns ( 23.68 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.761 ns 76.32 % " "Info: Total interconnect delay = 4.761 ns ( 76.32 % )" { } { } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "6.238 ns" { in1 state.s0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.238 ns" { in1 in1~combout state.s0 } { 0.000ns 0.000ns 4.761ns } { 0.000ns 0.804ns 0.673ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.656 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.656 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_A13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_A13; Fanout = 1; CLK Node = 'clk'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { clk } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.058 ns clk~clkctrl 2 COMB CLKCTRL_G10 2 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.058 ns; Loc. = CLKCTRL_G10; Fanout = 2; COMB Node = 'clk~clkctrl'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.113 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.548 ns) 2.656 ns state.s0 3 REG LCFF_X3_Y35_N7 1 " "Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.656 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "1.598 ns" { clk~clkctrl state.s0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 56.21 % " "Info: Total cell delay = 1.493 ns ( 56.21 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.163 ns 43.79 % " "Info: Total interconnect delay = 1.163 ns ( 43.79 % )" { } { } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s0 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "6.238 ns" { in1 state.s0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.238 ns" { in1 in1~combout state.s0 } { 0.000ns 0.000ns 4.761ns } { 0.000ns 0.804ns 0.673ns } } } { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s0 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out1 state.s0 6.782 ns register " "Info: tco from clock \"clk\" to destination pin \"out1\" through register \"state.s0\" is 6.782 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.656 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.656 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_A13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_A13; Fanout = 1; CLK Node = 'clk'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { clk } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.058 ns clk~clkctrl 2 COMB CLKCTRL_G10 2 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.058 ns; Loc. = CLKCTRL_G10; Fanout = 2; COMB Node = 'clk~clkctrl'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.113 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.548 ns) 2.656 ns state.s0 3 REG LCFF_X3_Y35_N7 1 " "Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.656 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "1.598 ns" { clk~clkctrl state.s0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 56.21 % " "Info: Total cell delay = 1.493 ns ( 56.21 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.163 ns 43.79 % " "Info: Total interconnect delay = 1.163 ns ( 43.79 % )" { } { } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s0 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns + " "Info: + Micro clock to output delay of source is 0.255 ns" { } { } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.871 ns + Longest register pin " "Info: + Longest register to pin delay is 3.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.s0 1 REG LCFF_X3_Y35_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { state.s0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.447 ns) 0.761 ns Select~14 2 COMB LCCOMB_X3_Y35_N0 2 " "Info: 2: + IC(0.314 ns) + CELL(0.447 ns) = 0.761 ns; Loc. = LCCOMB_X3_Y35_N0; Fanout = 2; COMB Node = 'Select~14'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "0.761 ns" { state.s0 Select~14 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.572 ns) + CELL(2.538 ns) 3.871 ns out1 3 PIN PIN_A5 0 " "Info: 3: + IC(0.572 ns) + CELL(2.538 ns) = 3.871 ns; Loc. = PIN_A5; Fanout = 0; PIN Node = 'out1'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "3.110 ns" { Select~14 out1 } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.985 ns 77.11 % " "Info: Total cell delay = 2.985 ns ( 77.11 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.886 ns 22.89 % " "Info: Total interconnect delay = 0.886 ns ( 22.89 % )" { } { } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "3.871 ns" { state.s0 Select~14 out1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.871 ns" { state.s0 Select~14 out1 } { 0.000ns 0.314ns 0.572ns } { 0.000ns 0.447ns 2.538ns } } } } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "2.656 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.656 ns" { clk clk~combout clk~clkctrl state.s0 } { 0.000ns 0.000ns 0.113ns 1.050ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "3.871 ns" { state.s0 Select~14 out1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.871 ns" { state.s0 Select~14 out1 } { 0.000ns 0.314ns 0.572ns } { 0.000ns 0.447ns 2.538ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "in1 out1 8.839 ns Longest " "Info: Longest tpd from source pin \"in1\" to destination pin \"out1\" is 8.839 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.804 ns) 0.804 ns in1 1 PIN PIN_A4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.804 ns) = 0.804 ns; Loc. = PIN_A4; Fanout = 2; PIN Node = 'in1'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "" { in1 } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.772 ns) + CELL(0.153 ns) 5.729 ns Select~14 2 COMB LCCOMB_X3_Y35_N0 2 " "Info: 2: + IC(4.772 ns) + CELL(0.153 ns) = 5.729 ns; Loc. = LCCOMB_X3_Y35_N0; Fanout = 2; COMB Node = 'Select~14'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "4.925 ns" { in1 Select~14 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.572 ns) + CELL(2.538 ns) 8.839 ns out1 3 PIN PIN_A5 0 " "Info: 3: + IC(0.572 ns) + CELL(2.538 ns) = 8.839 ns; Loc. = PIN_A5; Fanout = 0; PIN Node = 'out1'" { } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "3.110 ns" { Select~14 out1 } "NODE_NAME" } "" } } { "stmch1.vhd" "" { Text "C:/微机实验报告/evelyn/ex (3)/stmch1.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.495 ns 39.54 % " "Info: Total cell delay = 3.495 ns ( 39.54 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.344 ns 60.46 % " "Info: Total interconnect delay = 5.344 ns ( 60.46 % )" { } { } 0} } { { "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" "" { Report "C:/微机实验报告/evelyn/ex (3)/db/stmch1_cmp.qrpt" Compiler "stmch1" "UNKNOWN" "V1" "C:/微机实验报告/evelyn/ex (3)/db/stmch1.quartus_db" { Floorplan "C:/微机实验报告/evelyn/ex (3)/" "" "8.839 ns" { in1 Select~14 out1 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "8.839 ns" { in1 in1~combout Select~14 out1 } { 0.000ns 0.000ns 4.772ns 0.572ns } { 0.000ns 0.804ns 0.153ns 2.538ns } } } } 0}
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