stmch1.tan.rpt

4位可逆计数器：将50MHz的时钟进行 分频后的结果作为时钟控制

; Slack ; Required tco ; Actual tco ; From     ; To   ; From Clock ;
+-------+--------------+------------+----------+------+------------+
; N/A   ; None         ; 6.782 ns   ; state.s0 ; out1 ; clk        ;
; N/A   ; None         ; 6.350 ns   ; state.s1 ; out1 ; clk        ;
+-------+--------------+------------+----------+------+------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 8.839 ns        ; in1  ; out1 ;
+-------+-------------------+-----------------+------+------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -2.989 ns ; in1  ; state.s1 ; clk      ;
; N/A           ; None        ; -3.412 ns ; in1  ; state.s0 ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jan 04 17:22:12 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off stmch1 -c stmch1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 464.04 MHz between source register "state.s0" and destination register "state.s1"
    Info: fmax restricted to clock pin edge rate 2.155 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.847 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'
            Info: 2: + IC(0.314 ns) + CELL(0.447 ns) = 0.761 ns; Loc. = LCCOMB_X3_Y35_N0; Fanout = 2; COMB Node = 'Select~14'
            Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 0.847 ns; Loc. = LCFF_X3_Y35_N1; Fanout = 2; REG Node = 'state.s1'
            Info: Total cell delay = 0.533 ns ( 62.93 % )
            Info: Total interconnect delay = 0.314 ns ( 37.07 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.656 ns
                Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_A13; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.058 ns; Loc. = CLKCTRL_G10; Fanout = 2; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.656 ns; Loc. = LCFF_X3_Y35_N1; Fanout = 2; REG Node = 'state.s1'
                Info: Total cell delay = 1.493 ns ( 56.21 % )
                Info: Total interconnect delay = 1.163 ns ( 43.79 % )
            Info: - Longest clock path from clock "clk" to source register is 2.656 ns
                Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_A13; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.058 ns; Loc. = CLKCTRL_G10; Fanout = 2; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.656 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'
                Info: Total cell delay = 1.493 ns ( 56.21 % )
                Info: Total interconnect delay = 1.163 ns ( 43.79 % )
        Info: + Micro clock to output delay of source is 0.255 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "state.s0" (data pin = "in1", clock pin = "clk") is 3.546 ns
    Info: + Longest pin to register delay is 6.238 ns
        Info: 1: + IC(0.000 ns) + CELL(0.804 ns) = 0.804 ns; Loc. = PIN_A4; Fanout = 2; PIN Node = 'in1'
        Info: 2: + IC(4.761 ns) + CELL(0.673 ns) = 6.238 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'
        Info: Total cell delay = 1.477 ns ( 23.68 % )
        Info: Total interconnect delay = 4.761 ns ( 76.32 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.656 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_A13; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.058 ns; Loc. = CLKCTRL_G10; Fanout = 2; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.656 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'
        Info: Total cell delay = 1.493 ns ( 56.21 % )
        Info: Total interconnect delay = 1.163 ns ( 43.79 % )
Info: tco from clock "clk" to destination pin "out1" through register "state.s0" is 6.782 ns
    Info: + Longest clock path from clock "clk" to source register is 2.656 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_A13; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.058 ns; Loc. = CLKCTRL_G10; Fanout = 2; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.656 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'
        Info: Total cell delay = 1.493 ns ( 56.21 % )
        Info: Total interconnect delay = 1.163 ns ( 43.79 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Longest register to pin delay is 3.871 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X3_Y35_N7; Fanout = 1; REG Node = 'state.s0'
        Info: 2: + IC(0.314 ns) + CELL(0.447 ns) = 0.761 ns; Loc. = LCCOMB_X3_Y35_N0; Fanout = 2; COMB Node = 'Select~14'
        Info: 3: + IC(0.572 ns) + CELL(2.538 ns) = 3.871 ns; Loc. = PIN_A5; Fanout = 0; PIN Node = 'out1'
        Info: Total cell delay = 2.985 ns ( 77.11 % )
        Info: Total interconnect delay = 0.886 ns ( 22.89 % )
Info: Longest tpd from source pin "in1" to destination pin "out1" is 8.839 ns
    Info: 1: + IC(0.000 ns) + CELL(0.804 ns) = 0.804 ns; Loc. = PIN_A4; Fanout = 2; PIN Node = 'in1'
    Info: 2: + IC(4.772 ns) + CELL(0.153 ns) = 5.729 ns; Loc. = LCCOMB_X3_Y35_N0; Fanout = 2; COMB Node = 'Select~14'
    Info: 3: + IC(0.572 ns) + CELL(2.538 ns) = 8.839 ns; Loc. = PIN_A5; Fanout = 0; PIN Node = 'out1'
    Info: Total cell delay = 3.495 ns ( 39.54 % )
    Info: Total interconnect delay = 5.344 ns ( 60.46 % )
Info: th for register "state.s1" (data pin = "in1", clock pin = "clk") is -2.989 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.656 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_A13; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.058 ns; Loc. = CLKCTRL_G10; Fanout = 2; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.656 ns; Loc. = LCFF_X3_Y35_N1; Fanout = 2; REG Node = 'state.s1'
        Info: Total cell delay = 1.493 ns ( 56.21 % )
        Info: Total interconnect delay = 1.163 ns ( 43.79 % )
    Info: + Micro hold delay of destination is 0.170 ns
    Info: - Shortest pin to register delay is 5.815 ns
        Info: 1: + IC(0.000 ns) + CELL(0.804 ns) = 0.804 ns; Loc. = PIN_A4; Fanout = 2; PIN Node = 'in1'
        Info: 2: + IC(4.772 ns) + CELL(0.153 ns) = 5.729 ns; Loc. = LCCOMB_X3_Y35_N0; Fanout = 2; COMB Node = 'Select~14'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 5.815 ns; Loc. = LCFF_X3_Y35_N1; Fanout = 2; REG Node = 'state.s1'
        Info: Total cell delay = 1.043 ns ( 17.94 % )
        Info: Total interconnect delay = 4.772 ns ( 82.06 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jan 04 17:22:13 2008
    Info: Elapsed time: 00:00:01