rom.tan.rpt

基于ROM的正弦波发生器的设计:使用MATLAB得到这64个波形数据

; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[3] ; lock:u2|outdata[1] ; clk        ; clk      ; None                        ; None                      ; 1.722 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[2] ; lock:u2|outdata[7] ; clk        ; clk      ; None                        ; None                      ; 1.703 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; lock:u2|outdata[7] ; clk        ; clk      ; None                        ; None                      ; 1.663 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[5] ; lock:u2|outdata[1] ; clk        ; clk      ; None                        ; None                      ; 1.628 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[5] ; lock:u2|outdata[2] ; clk        ; clk      ; None                        ; None                      ; 1.595 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; lock:u2|outdata[0] ; clk        ; clk      ; None                        ; None                      ; 1.576 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; lock:u2|outdata[3] ; clk        ; clk      ; None                        ; None                      ; 1.570 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; counter:u0|m[5]    ; clk        ; clk      ; None                        ; None                      ; 1.523 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[1] ; lock:u2|outdata[7] ; clk        ; clk      ; None                        ; None                      ; 1.514 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; lock:u2|outdata[1] ; clk        ; clk      ; None                        ; None                      ; 1.473 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; counter:u0|m[4]    ; clk        ; clk      ; None                        ; None                      ; 1.472 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[2] ; counter:u0|m[5]    ; clk        ; clk      ; None                        ; None                      ; 1.424 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; counter:u0|m[3]    ; clk        ; clk      ; None                        ; None                      ; 1.421 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[1] ; counter:u0|m[5]    ; clk        ; clk      ; None                        ; None                      ; 1.415 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[3] ; lock:u2|outdata[7] ; clk        ; clk      ; None                        ; None                      ; 1.399 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[2] ; counter:u0|m[4]    ; clk        ; clk      ; None                        ; None                      ; 1.373 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; counter:u0|m[2]    ; clk        ; clk      ; None                        ; None                      ; 1.370 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[1] ; counter:u0|m[4]    ; clk        ; clk      ; None                        ; None                      ; 1.364 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[3] ; counter:u0|m[5]    ; clk        ; clk      ; None                        ; None                      ; 1.334 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; lock:u2|outdata[2] ; clk        ; clk      ; None                        ; None                      ; 1.330 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[5] ; lock:u2|outdata[7] ; clk        ; clk      ; None                        ; None                      ; 1.323 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[2] ; counter:u0|m[3]    ; clk        ; clk      ; None                        ; None                      ; 1.322 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; counter:u0|m[1]    ; clk        ; clk      ; None                        ; None                      ; 1.319 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[1] ; counter:u0|m[3]    ; clk        ; clk      ; None                        ; None                      ; 1.313 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[3] ; counter:u0|m[4]    ; clk        ; clk      ; None                        ; None                      ; 1.283 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; counter:u0|m[5]    ; clk        ; clk      ; None                        ; None                      ; 1.277 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; lock:u2|outdata[7] ; clk        ; clk      ; None                        ; None                      ; 1.272 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[1] ; counter:u0|m[2]    ; clk        ; clk      ; None                        ; None                      ; 1.262 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; lock:u2|outdata[5] ; clk        ; clk      ; None                        ; None                      ; 1.157 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[5] ; lock:u2|outdata[6] ; clk        ; clk      ; None                        ; None                      ; 1.082 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[5] ; lock:u2|outdata[0] ; clk        ; clk      ; None                        ; None                      ; 1.082 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[5] ; lock:u2|outdata[4] ; clk        ; clk      ; None                        ; None                      ; 1.081 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[2] ; counter:u0|m[2]    ; clk        ; clk      ; None                        ; None                      ; 0.934 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; counter:u0|m[0]    ; clk        ; clk      ; None                        ; None                      ; 0.931 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[3] ; counter:u0|m[3]    ; clk        ; clk      ; None                        ; None                      ; 0.897 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[2] ; lock:u2|outdata[4] ; clk        ; clk      ; None                        ; None                      ; 0.893 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; counter:u0|m[4]    ; clk        ; clk      ; None                        ; None                      ; 0.891 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; lock:u2|outdata[0] ; clk        ; clk      ; None                        ; None                      ; 0.875 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[0] ; lock:u2|outdata[6] ; clk        ; clk      ; None                        ; None                      ; 0.874 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[1] ; counter:u0|m[1]    ; clk        ; clk      ; None                        ; None                      ; 0.876 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[5] ; lock:u2|outdata[5] ; clk        ; clk      ; None                        ; None                      ; 0.801 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[5] ; counter:u0|m[5]    ; clk        ; clk      ; None                        ; None                      ; 0.601 ns                ;
+-------+------------------------------------------------+-----------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------+
; tco                                                                           ;
+-------+--------------+------------+--------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To      ; From Clock ;
+-------+--------------+------------+--------------------+---------+------------+
; N/A   ; None         ; 6.344 ns   ; lock:u2|outdata[7] ; wave[7] ; clk        ;
; N/A   ; None         ; 6.334 ns   ; lock:u2|outdata[0] ; wave[0] ; clk        ;
; N/A   ; None         ; 6.327 ns   ; lock:u2|outdata[5] ; wave[5] ; clk        ;
; N/A   ; None         ; 6.309 ns   ; lock:u2|outdata[2] ; wave[2] ; clk        ;
; N/A   ; None         ; 6.306 ns   ; lock:u2|outdata[6] ; wave[6] ; clk        ;
; N/A   ; None         ; 6.083 ns   ; lock:u2|outdata[4] ; wave[4] ; clk        ;
; N/A   ; None         ; 6.083 ns   ; lock:u2|outdata[1] ; wave[1] ; clk        ;
; N/A   ; None         ; 6.081 ns   ; lock:u2|outdata[3] ; wave[3] ; clk        ;
+-------+--------------+------------+--------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
    Info: Processing started: Wed Dec 19 12:48:42 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off rom -c rom --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 302.39 MHz between source register "counter:u0|m[1]" and destination register "lock:u2|outdata[3]" (period= 3.307 ns)
    Info: + Longest register to register delay is 3.086 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y35_N23; Fanout = 20; REG Node = 'counter:u0|m[1]'
        Info: 2: + IC(0.931 ns) + CELL(0.447 ns) = 1.378 ns; Loc. = LCCOMB_X34_Y35_N26; Fanout = 1; COMB Node = 'rom_1:u1|data[3]~1410'
        Info: 3: + IC(0.464 ns) + CELL(0.447 ns) = 2.289 ns; Loc. = LCCOMB_X34_Y35_N10; Fanout = 1; COMB Node = 'rom_1:u1|data[3]~1412'
        Info: 4: + IC(0.264 ns) + CELL(0.447 ns) = 3.000 ns; Loc. = LCCOMB_X34_Y35_N0; Fanout = 1; COMB Node = 'rom_1:u1|data[3]~1414'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 3.086 ns; Loc. = LCFF_X34_Y35_N1; Fanout = 1; REG Node = 'lock:u2|outdata[3]'
        Info: Total cell delay = 1.427 ns ( 46.24 % )
        Info: Total interconnect delay = 1.659 ns ( 53.76 % )
    Info: - Smallest clock skew is -0.002 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.659 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G3; Fanout = 14; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.048 ns) + CELL(0.548 ns) = 2.659 ns; Loc. = LCFF_X34_Y35_N1; Fanout = 1; REG Node = 'lock:u2|outdata[3]'
            Info: Total cell delay = 1.493 ns ( 56.15 % )
            Info: Total interconnect delay = 1.166 ns ( 43.85 % )
        Info: - Longest clock path from clock "clk" to source register is 2.661 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G3; Fanout = 14; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.050 ns) + CELL(0.548 ns) = 2.661 ns; Loc. = LCFF_X35_Y35_N23; Fanout = 20; REG Node = 'counter:u0|m[1]'
            Info: Total cell delay = 1.493 ns ( 56.11 % )
            Info: Total interconnect delay = 1.168 ns ( 43.89 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk" to destination pin "wave[7]" through register "lock:u2|outdata[7]" is 6.344 ns
    Info: + Longest clock path from clock "clk" to source register is 2.659 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G3; Fanout = 14; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.048 ns) + CELL(0.548 ns) = 2.659 ns; Loc. = LCFF_X33_Y35_N21; Fanout = 1; REG Node = 'lock:u2|outdata[7]'
        Info: Total cell delay = 1.493 ns ( 56.15 % )
        Info: Total interconnect delay = 1.166 ns ( 43.85 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Longest register to pin delay is 3.430 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y35_N21; Fanout = 1; REG Node = 'lock:u2|outdata[7]'
        Info: 2: + IC(0.892 ns) + CELL(2.538 ns) = 3.430 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'wave[7]'
        Info: Total cell delay = 2.538 ns ( 73.99 % )
        Info: Total interconnect delay = 0.892 ns ( 26.01 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 19 12:48:42 2007
    Info: Elapsed time: 00:00:01