rom.tan.rpt

基于ROM的正弦波发生器的设计:使用MATLAB得到这64个波形数据

Timing Analyzer report for rom
Wed Dec 19 12:48:42 2007
Version 5.0 Build 148 04/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                  ;
+------------------------------+-------+---------------+----------------------------------+--------------------+--------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From               ; To                 ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------------+--------------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 6.344 ns                         ; lock:u2|outdata[7] ; wave[7]            ; clk        ;          ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 302.39 MHz ( period = 3.307 ns ) ; counter:u0|m[1]    ; lock:u2|outdata[3] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                    ;                    ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------------+--------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                        ;
+-------+------------------------------------------------+-----------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From            ; To                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 302.39 MHz ( period = 3.307 ns )               ; counter:u0|m[1] ; lock:u2|outdata[3] ; clk        ; clk      ; None                        ; None                      ; 3.086 ns                ;
; N/A   ; 333.11 MHz ( period = 3.002 ns )               ; counter:u0|m[0] ; lock:u2|outdata[3] ; clk        ; clk      ; None                        ; None                      ; 2.781 ns                ;
; N/A   ; 347.71 MHz ( period = 2.876 ns )               ; counter:u0|m[3] ; lock:u2|outdata[3] ; clk        ; clk      ; None                        ; None                      ; 2.655 ns                ;
; N/A   ; 366.30 MHz ( period = 2.730 ns )               ; counter:u0|m[2] ; lock:u2|outdata[3] ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A   ; 387.15 MHz ( period = 2.583 ns )               ; counter:u0|m[0] ; lock:u2|outdata[2] ; clk        ; clk      ; None                        ; None                      ; 2.364 ns                ;
; N/A   ; 388.05 MHz ( period = 2.577 ns )               ; counter:u0|m[1] ; lock:u2|outdata[5] ; clk        ; clk      ; None                        ; None                      ; 2.356 ns                ;
; N/A   ; 389.86 MHz ( period = 2.565 ns )               ; counter:u0|m[1] ; lock:u2|outdata[4] ; clk        ; clk      ; None                        ; None                      ; 2.344 ns                ;
; N/A   ; 396.04 MHz ( period = 2.525 ns )               ; counter:u0|m[1] ; lock:u2|outdata[2] ; clk        ; clk      ; None                        ; None                      ; 2.306 ns                ;
; N/A   ; 414.77 MHz ( period = 2.411 ns )               ; counter:u0|m[1] ; lock:u2|outdata[6] ; clk        ; clk      ; None                        ; None                      ; 2.190 ns                ;
; N/A   ; 415.45 MHz ( period = 2.407 ns )               ; counter:u0|m[1] ; lock:u2|outdata[0] ; clk        ; clk      ; None                        ; None                      ; 2.186 ns                ;
; N/A   ; 418.06 MHz ( period = 2.392 ns )               ; counter:u0|m[2] ; lock:u2|outdata[2] ; clk        ; clk      ; None                        ; None                      ; 2.173 ns                ;
; N/A   ; 419.46 MHz ( period = 2.384 ns )               ; counter:u0|m[3] ; lock:u2|outdata[6] ; clk        ; clk      ; None                        ; None                      ; 2.163 ns                ;
; N/A   ; 438.40 MHz ( period = 2.281 ns )               ; counter:u0|m[2] ; lock:u2|outdata[5] ; clk        ; clk      ; None                        ; None                      ; 2.060 ns                ;
; N/A   ; 441.70 MHz ( period = 2.264 ns )               ; counter:u0|m[3] ; lock:u2|outdata[2] ; clk        ; clk      ; None                        ; None                      ; 2.045 ns                ;
; N/A   ; 442.48 MHz ( period = 2.260 ns )               ; counter:u0|m[0] ; lock:u2|outdata[1] ; clk        ; clk      ; None                        ; None                      ; 2.041 ns                ;
; N/A   ; 442.67 MHz ( period = 2.259 ns )               ; counter:u0|m[0] ; lock:u2|outdata[4] ; clk        ; clk      ; None                        ; None                      ; 2.038 ns                ;
; N/A   ; 450.65 MHz ( period = 2.219 ns )               ; counter:u0|m[2] ; lock:u2|outdata[6] ; clk        ; clk      ; None                        ; None                      ; 1.998 ns                ;
; N/A   ; 454.34 MHz ( period = 2.201 ns )               ; counter:u0|m[1] ; lock:u2|outdata[1] ; clk        ; clk      ; None                        ; None                      ; 1.982 ns                ;
; N/A   ; 464.04 MHz ( period = 2.155 ns )               ; counter:u0|m[3] ; lock:u2|outdata[5] ; clk        ; clk      ; None                        ; None                      ; 1.934 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[3] ; lock:u2|outdata[4] ; clk        ; clk      ; None                        ; None                      ; 1.914 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[2] ; lock:u2|outdata[0] ; clk        ; clk      ; None                        ; None                      ; 1.884 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; lock:u2|outdata[6] ; clk        ; clk      ; None                        ; None                      ; 1.874 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[5] ; lock:u2|outdata[3] ; clk        ; clk      ; None                        ; None                      ; 1.849 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[2] ; lock:u2|outdata[1] ; clk        ; clk      ; None                        ; None                      ; 1.850 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[3] ; lock:u2|outdata[0] ; clk        ; clk      ; None                        ; None                      ; 1.757 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; lock:u2|outdata[5] ; clk        ; clk      ; None                        ; None                      ; 1.754 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; counter:u0|m[4] ; lock:u2|outdata[4] ; clk        ; clk      ; None                        ; None                      ; 1.733 ns                ;