sevenseg_case.tan.rpt

sevenseg_case verilog code

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Apr 09 19:03:36 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sevenseg_case -c sevenseg_case
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "up_down" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk_div" as buffer
Info: Clock "clk" has Internal fmax of 100.05 MHz between source register "counter[22]" and destination register "counter[0]" (period= 9.995 ns)
    Info: + Longest register to register delay is 9.397 ns
        Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC6_8_O1; Fanout = 3; REG Node = 'counter[22]'
        Info: 2: + IC(1.169 ns) + CELL(1.154 ns) = 2.532 ns; Loc. = LC3_7_O1; Fanout = 1; COMB Node = 'LessThan~587'
        Info: 3: + IC(1.180 ns) + CELL(0.899 ns) = 4.611 ns; Loc. = LC1_5_O1; Fanout = 1; COMB Node = 'LessThan~592'
        Info: 4: + IC(0.000 ns) + CELL(0.689 ns) = 5.300 ns; Loc. = LC2_5_O1; Fanout = 26; COMB Node = 'LessThan~590'
        Info: 5: + IC(3.453 ns) + CELL(0.644 ns) = 9.397 ns; Loc. = LC4_4_O1; Fanout = 2; REG Node = 'counter[0]'
        Info: Total cell delay = 3.595 ns ( 38.26 % )
        Info: Total interconnect delay = 5.802 ns ( 61.74 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.734 ns
            Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_L6; Fanout = 26; CLK Node = 'clk'
            Info: 2: + IC(1.361 ns) + CELL(0.000 ns) = 2.734 ns; Loc. = LC4_4_O1; Fanout = 2; REG Node = 'counter[0]'
            Info: Total cell delay = 1.373 ns ( 50.22 % )
            Info: Total interconnect delay = 1.361 ns ( 49.78 % )
        Info: - Longest clock path from clock "clk" to source register is 2.734 ns
            Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_L6; Fanout = 26; CLK Node = 'clk'
            Info: 2: + IC(1.361 ns) + CELL(0.000 ns) = 2.734 ns; Loc. = LC6_8_O1; Fanout = 3; REG Node = 'counter[22]'
            Info: Total cell delay = 1.373 ns ( 50.22 % )
            Info: Total interconnect delay = 1.361 ns ( 49.78 % )
    Info: + Micro clock to output delay of source is 0.434 ns
    Info: + Micro setup delay of destination is 0.164 ns
Info: Clock "up_down" Internal fmax is restricted to 220.95 MHz between source register "udreg" and destination register "udreg"
    Info: fmax restricted to clock pin edge rate 4.526 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.687 ns
            Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC3_15_Z2; Fanout = 9; REG Node = 'udreg'
            Info: 2: + IC(0.284 ns) + CELL(0.194 ns) = 0.687 ns; Loc. = LC3_15_Z2; Fanout = 9; REG Node = 'udreg'
            Info: Total cell delay = 0.403 ns ( 58.66 % )
            Info: Total interconnect delay = 0.284 ns ( 41.34 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "up_down" to destination register is 7.152 ns
                Info: 1: + IC(0.000 ns) + CELL(1.821 ns) = 1.821 ns; Loc. = PIN_W9; Fanout = 1; CLK Node = 'up_down'
                Info: 2: + IC(5.331 ns) + CELL(0.000 ns) = 7.152 ns; Loc. = LC3_15_Z2; Fanout = 9; REG Node = 'udreg'
                Info: Total cell delay = 1.821 ns ( 25.46 % )
                Info: Total interconnect delay = 5.331 ns ( 74.54 % )
            Info: - Longest clock path from clock "up_down" to source register is 7.152 ns
                Info: 1: + IC(0.000 ns) + CELL(1.821 ns) = 1.821 ns; Loc. = PIN_W9; Fanout = 1; CLK Node = 'up_down'
                Info: 2: + IC(5.331 ns) + CELL(0.000 ns) = 7.152 ns; Loc. = LC3_15_Z2; Fanout = 9; REG Node = 'udreg'
                Info: Total cell delay = 1.821 ns ( 25.46 % )
                Info: Total interconnect delay = 5.331 ns ( 74.54 % )
        Info: + Micro clock to output delay of source is 0.434 ns
        Info: + Micro setup delay of destination is 0.164 ns
Info: tco from clock "clk" to destination pin "seg[2]" through register "seg[2]~reg0" is 13.894 ns
    Info: + Longest clock path from clock "clk" to source register is 7.708 ns
        Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = PIN_L6; Fanout = 26; CLK Node = 'clk'
        Info: 2: + IC(1.360 ns) + CELL(0.643 ns) = 3.376 ns; Loc. = LC3_4_N1; Fanout = 11; REG Node = 'clk_div'
        Info: 3: + IC(4.332 ns) + CELL(0.000 ns) = 7.708 ns; Loc. = LC7_13_Z2; Fanout = 1; REG Node = 'seg[2]~reg0'
        Info: Total cell delay = 2.016 ns ( 26.15 % )
        Info: Total interconnect delay = 5.692 ns ( 73.85 % )
    Info: + Micro clock to output delay of source is 0.434 ns
    Info: + Longest register to pin delay is 5.752 ns
        Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC7_13_Z2; Fanout = 1; REG Node = 'seg[2]~reg0'
        Info: 2: + IC(2.892 ns) + CELL(2.651 ns) = 5.752 ns; Loc. = PIN_U8; Fanout = 0; PIN Node = 'seg[2]'
        Info: Total cell delay = 2.860 ns ( 49.72 % )
        Info: Total interconnect delay = 2.892 ns ( 50.28 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Apr 09 19:03:38 2009
    Info: Elapsed time: 00:00:03