sevenseg_case.fit.rpt

sevenseg_case verilog code

Fitter report for sevenseg_case
Thu Apr 09 19:03:31 2009
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Input Pins
  7. Output Pins
  8. All Package Pins
  9. Control Signals
 10. Global & Other Fast Signals
 11. Carry Chains
 12. Cascade Chains
 13. Non-Global High Fan-Out Signals
 14. Local Routing Interconnect
 15. MegaLAB Interconnect
 16. LAB External Interconnect
 17. MegaLAB Usage Summary
 18. Row Interconnect
 19. LAB Column Interconnect
 20. ESB Column Interconnect
 21. Fitter Resource Usage Summary
 22. Fitter Resource Utilization by Entity
 23. Delay Chain Summary
 24. I/O Bank Usage
 25. Pin-Out File
 26. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Fitter Summary                                                        ;
+-----------------------+-----------------------------------------------+
; Fitter Status         ; Successful - Thu Apr 09 19:03:31 2009         ;
; Quartus II Version    ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name         ; sevenseg_case                                 ;
; Top-level Entity Name ; sevenseg_case                                 ;
; Family                ; APEX20KE                                      ;
; Device                ; EP20K200EFC484-2X                             ;
; Timing Models         ; Final                                         ;
; Total logic elements  ; 46 / 8,320 ( < 1 % )                          ;
; Total pins            ; 10 / 376 ( 2 % )                              ;
; Total virtual pins    ; 0                                             ;
; Total memory bits     ; 0 / 106,496 ( 0 % )                           ;
; Total PLLs            ; 0 / 2 ( 0 % )                                 ;
+-----------------------+-----------------------------------------------+


+------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                ;
+------------------------------------------------------+--------------------+--------------------+
; Option                                               ; Setting            ; Default Value      ;
+------------------------------------------------------+--------------------+--------------------+
; Device                                               ; EP20K200EFC484-2X  ;                    ;
; Fitter Effort                                        ; Standard Fit       ; Auto Fit           ;
; SignalProbe signals routed during normal compilation ; Off                ; Off                ;
; Use smart compilation                                ; Off                ; Off                ;
; Placement Effort Multiplier                          ; 1.0                ; 1.0                ;
; Router Effort Multiplier                             ; 1.0                ; 1.0                ;
; Optimize Timing                                      ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing           ; On                 ; On                 ;
; Limit to One Fitting Attempt                         ; Off                ; Off                ;
; Final Placement Optimizations                        ; Automatically      ; Automatically      ;
; Fitter Initial Placement Seed                        ; 1                  ; 1                  ;
; Slow Slew Rate                                       ; Off                ; Off                ;
; PCI I/O                                              ; Off                ; Off                ;
; Turbo Bit                                            ; On                 ; On                 ;
; Auto Global Memory Control Signals                   ; Off                ; Off                ;
; Auto Global Clock                                    ; On                 ; On                 ;
; Auto Global Output Enable                            ; On                 ; On                 ;
; Auto Global Register Control Signals                 ; On                 ; On                 ;
+------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in C:/Documents and Settings/vlsilab/