audio_dac.vhd

Pacman 4 DE1-FPGA-Board

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY AUDIO_DAC IS 
	port
	(
	Sound_L		 : in  UNSIGNED(15 downto 0);
	Sound_R		 : in  UNSIGNED(15 downto 0);
	-- Audio Side
	oAUD_XCK	 : out STD_LOGIC;
	ioAUD_BCLK	 : inout STD_LOGIC;
	oAUD_DACDAT	 : out STD_LOGIC;
	oAUD_DACLRCK : out STD_LOGIC;
	oAUD_ADCLRCK : out STD_LOGIC;
	--	Control Signals					
	iCLK		 : in  STD_LOGIC;
	iRST_N		 : in  STD_LOGIC
	);
END AUDIO_DAC;

ARCHITECTURE A_DAC OF AUDIO_DAC  IS

---
CONSTANT REF_CLK	 : INTEGER := 18432000;	--	18.432	MHz
CONSTANT SAMPLE_RATE : INTEGER := 48000;	--	48		KHz
CONSTANT DATA_WIDTH	 : INTEGER := 16;		--	16		Bits
CONSTANT CHANNEL_NUM : INTEGER := 2;		--	Dual Channel
---
SIGNAL RCounter		: UNSIGNED(19 downto 0):= (others =>'0');
SIGNAL ResetDelay	: STD_LOGIC := '0';

SIGNAL BCK_DIV		: UNSIGNED(3 downto 0):= (others =>'0');
SIGNAL LRCK_1X_DIV	: UNSIGNED(8 downto 0):= (others =>'0');
SIGNAL SEL_Cont		: UNSIGNED(4 downto 0):= "11111";
SIGNAL Sound		: UNSIGNED(31 downto 0):= (others =>'0');
SIGNAL LRCK_1X		: STD_LOGIC := '0';
SIGNAL AUD_BCLK		: STD_LOGIC := '0';
---
BEGIN
oAUD_XCK	 <= iCLK;
ioAUD_BCLK 	 <= AUD_BCLK;
oAUD_DACLRCK <= LRCK_1X;
oAUD_ADCLRCK <= LRCK_1X;
oAUD_DACDAT	 <= Sound(to_integer(SEL_Cont));

	-- Reset-Delay
	process(iCLK,iRST_N)
	begin
	if(iRST_N = '0')then
		RCounter	<= (others => '0');
		ResetDelay	<= '0';
	else
		if(rising_edge(iCLK))then
			if(RCounter < X"FFFFF")then
				RCounter  	<= RCounter + 1;
				ResetDelay	<= '0';
			else
				ResetDelay <= '1';			
			end if;
		end if;
	end if;
	end process;

	-- AUD_DACLRCK Generator
	process(iCLK,ResetDelay)
	begin
	if(ResetDelay = '0')then
		BCK_DIV		<= (others => '0');
		AUD_BCLK		<=	'0';		
	else
		if(rising_edge(iCLK))then
			if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1)then
				BCK_DIV		<= (others => '0');		
				AUD_BCLK	<=	not AUD_BCLK;
			else
				BCK_DIV		<=	BCK_DIV+1;
			end if;
		end if;
	end if;
	end process;

	-- AUD_LRCK Generator
	process(iCLK,ResetDelay)
	begin
	if(ResetDelay = '0')then
		LRCK_1X_DIV	<= (others => '0');
		LRCK_1X		<=	'0';
		Sound		<= (others =>'0');		
	else
		if(rising_edge(iCLK))then
			if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1)then
				LRCK_1X_DIV	<= (others => '0');			
				LRCK_1X		<=	not LRCK_1X;

				Sound(31 downto 16) <= Sound_R(15 downto 0);
				Sound(15 downto  0) <= Sound_L(15 downto 0);					
			else
				LRCK_1X_DIV	<=	LRCK_1X_DIV+1;
			end if;
		end if;
	end if;
	end process;

	-- 16 Bits PISO MSB First
	process(AUD_BCLK,ResetDelay)
	begin
	if(ResetDelay = '0')then
		SEL_Cont <= "11111";
	elsif(falling_edge(AUD_BCLK))then
		SEL_Cont <=	SEL_Cont-1;
	end if;
	end process;


END A_DAC;