fifo.tan.qmsg

先进先出存储电路fifo

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0 memory lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\] 196.97 MHz 5.077 ns Internal " "Info: Clock \"clk\" has Internal fmax of 196.97 MHz between source memory \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0\" and destination memory \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\]\" (period= 5.077 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0 1 MEM M4K_X33_Y14 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y14; Fanout = 8; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\] 2 MEM M4K_X33_Y14 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.015 ns - Smallest " "Info: - Smallest clock skew is -0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.233 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 8.233 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_240 77 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.055 ns) + CELL(0.703 ns) 8.233 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\] 2 MEM M4K_X33_Y14 1 " "Info: 2: + IC(6.055 ns) + CELL(0.703 ns) = 8.233 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.758 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.178 ns ( 26.45 % ) " "Info: Total cell delay = 2.178 ns ( 26.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.055 ns ( 73.55 % ) " "Info: Total interconnect delay = 6.055 ns ( 73.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.703ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.248 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 8.248 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_240 77 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.055 ns) + CELL(0.718 ns) 8.248 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0 2 MEM M4K_X33_Y14 8 " "Info: 2: + IC(6.055 ns) + CELL(0.718 ns) = 8.248 ns; Loc. = M4K_X33_Y14; Fanout = 8; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.773 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 26.59 % ) " "Info: Total cell delay = 2.193 ns ( 26.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.055 ns ( 73.41 % ) " "Info: Total interconnect delay = 6.055 ns ( 73.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.248 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.248 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.718ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.703ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.248 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.248 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.718ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.703ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.248 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.248 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.718ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff wr clk 7.238 ns register " "Info: tsu for register \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff\" (data pin = \"wr\", clock pin = \"clk\") is 7.238 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.442 ns + Longest pin register " "Info: + Longest pin to register delay is 15.442 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns wr 1 PIN PIN_239 24 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_239; Fanout = 24; PIN Node = 'wr'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 160 -40 128 176 "wr" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(10.297 ns) + CELL(0.114 ns) 11.886 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|valid_wreq~26 2 COMB LC_X37_Y12_N9 25 " "Info: 2: + IC(10.297 ns) + CELL(0.114 ns) = 11.886 ns; Loc. = LC_X37_Y12_N9; Fanout = 25; COMB Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|valid_wreq~26'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.411 ns" { wr lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 } "NODE_NAME" } } { "db/a_dpfifo_ee21.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/a_dpfifo_ee21.tdf" 73 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.389 ns) + CELL(0.442 ns) 13.717 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|_~66 3 COMB LC_X36_Y14_N8 2 " "Info: 3: + IC(1.389 ns) + CELL(0.442 ns) = 13.717 ns; Loc. = LC_X36_Y14_N8; Fanout = 2; COMB Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|_~66'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.831 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 } "NODE_NAME" } } { "db/scfifo_7821.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/scfifo_7821.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.247 ns) + CELL(0.478 ns) 15.442 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff 4 REG LC_X37_Y13_N0 21 " "Info: 4: + IC(1.247 ns) + CELL(0.478 ns) = 15.442 ns; Loc. = LC_X37_Y13_N0; Fanout = 21; REG Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.725 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_ee21.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/a_dpfifo_ee21.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.509 ns ( 16.25 % ) " "Info: Total cell delay = 2.509 ns ( 16.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.933 ns ( 83.75 % ) " "Info: Total interconnect delay = 12.933 ns ( 83.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.442 ns" { wr lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.442 ns" { wr {} wr~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff {} } { 0.000ns 0.000ns 10.297ns 1.389ns 1.247ns } { 0.000ns 1.475ns 0.114ns 0.442ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/a_dpfifo_ee21.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/a_dpfifo_ee21.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.241 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_240 77 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.055 ns) + CELL(0.711 ns) 8.241 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff 2 REG LC_X37_Y13_N0 21 " "Info: 2: + IC(6.055 ns) + CELL(0.711 ns) = 8.241 ns; Loc. = LC_X37_Y13_N0; Fanout = 21; REG Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.766 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_ee21.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/a_dpfifo_ee21.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 26.53 % ) " "Info: Total cell delay = 2.186 ns ( 26.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.055 ns ( 73.47 % ) " "Info: Total interconnect delay = 6.055 ns ( 73.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.241 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.241 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.442 ns" { wr lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.442 ns" { wr {} wr~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff {} } { 0.000ns 0.000ns 10.297ns 1.389ns 1.247ns } { 0.000ns 1.475ns 0.114ns 0.442ns 0.478ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.241 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.241 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[0\] lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\] 16.453 ns memory " "Info: tco from clock \"clk\" to destination pin \"q\[0\]\" through memory \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\]\" is 16.453 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.233 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 8.233 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_240 77 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.055 ns) + CELL(0.703 ns) 8.233 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\] 2 MEM M4K_X33_Y14 1 " "Info: 2: + IC(6.055 ns) + CELL(0.703 ns) = 8.233 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.758 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.178 ns ( 26.45 % ) " "Info: Total cell delay = 2.178 ns ( 26.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.055 ns ( 73.55 % ) " "Info: Total interconnect delay = 6.055 ns ( 73.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.703ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.570 ns + Longest memory pin " "Info: + Longest memory to pin delay is 7.570 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\] 1 MEM M4K_X33_Y14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.342 ns) + CELL(2.124 ns) 7.570 ns q\[0\] 2 PIN PIN_13 0 " "Info: 2: + IC(5.342 ns) + CELL(2.124 ns) = 7.570 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.466 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] q[0] } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 136 400 576 152 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.228 ns ( 29.43 % ) " "Info: Total cell delay = 2.228 ns ( 29.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.342 ns ( 70.57 % ) " "Info: Total interconnect delay = 5.342 ns ( 70.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.570 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] q[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.570 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] {} q[0] {} } { 0.000ns 5.342ns } { 0.104ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.703ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.570 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] q[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.570 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] {} q[0] {} } { 0.000ns 5.342ns } { 0.104ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg2 D\[5\] clk -2.328 ns memory " "Info: th for memory \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg2\" (data pin = \"D\[5\]\", clock pin = \"clk\") is -2.328 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.252 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to destination memory is 8.252 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_240 77 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.055 ns) + CELL(0.722 ns) 8.252 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg2 2 MEM M4K_X33_Y14 1 " "Info: 2: + IC(6.055 ns) + CELL(0.722 ns) = 8.252 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.777 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.197 ns ( 26.62 % ) " "Info: Total cell delay = 2.197 ns ( 26.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.055 ns ( 73.38 % ) " "Info: Total interconnect delay = 6.055 ns ( 73.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.252 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.252 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.055 ns + " "Info: + Micro hold delay of destination is 0.055 ns" {  } { { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.635 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 10.635 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns D\[5\] 1 PIN PIN_7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_7; Fanout = 1; PIN Node = 'D\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[5] } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 136 -40 128 152 "D\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.810 ns) + CELL(0.356 ns) 10.635 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg2 2 MEM M4K_X33_Y14 1 " "Info: 2: + IC(8.810 ns) + CELL(0.356 ns) = 10.635 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.166 ns" { D[5] lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.825 ns ( 17.16 % ) " "Info: Total cell delay = 1.825 ns ( 17.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.810 ns ( 82.84 % ) " "Info: Total interconnect delay = 8.810 ns ( 82.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.635 ns" { D[5] lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.635 ns" { D[5] {} D[5]~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 {} } { 0.000ns 0.000ns 8.810ns } { 0.000ns 1.469ns 0.356ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.252 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.252 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 {} } { 0.000ns 0.000ns 6.055ns } { 0.000ns 1.475ns 0.722ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.635 ns" { D[5] lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.635 ns" { D[5] {} D[5]~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg2 {} } { 0.000ns 0.000ns 8.810ns } { 0.000ns 1.469ns 0.356ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}