prev_cmp_fifo.tan.qmsg

先进先出存储电路fifo

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0 memory lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\] 196.97 MHz 5.077 ns Internal " "Info: Clock \"clk\" has Internal fmax of 196.97 MHz between source memory \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0\" and destination memory \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\]\" (period= 5.077 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0 1 MEM M4K_X19_Y16 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X19_Y16; Fanout = 8; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\] 2 MEM M4K_X19_Y16 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X19_Y16; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.015 ns - Smallest " "Info: - Smallest clock skew is -0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.238 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 3.238 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.703 ns) 3.238 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\] 2 MEM M4K_X19_Y16 1 " "Info: 2: + IC(1.066 ns) + CELL(0.703 ns) = 3.238 ns; Loc. = M4K_X19_Y16; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.769 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.172 ns ( 67.08 % ) " "Info: Total cell delay = 2.172 ns ( 67.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.92 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.238 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.238 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.703ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.253 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 3.253 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.718 ns) 3.253 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0 2 MEM M4K_X19_Y16 8 " "Info: 2: + IC(1.066 ns) + CELL(0.718 ns) = 3.253 ns; Loc. = M4K_X19_Y16; Fanout = 8; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~portb_address_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.784 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.187 ns ( 67.23 % ) " "Info: Total cell delay = 2.187 ns ( 67.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.77 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.253 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.253 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.718ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.238 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.238 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.703ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.253 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.253 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.718ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.238 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.238 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[7] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.703ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.253 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.253 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg0 {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.718ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff wr clk 9.125 ns register " "Info: tsu for register \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff\" (data pin = \"wr\", clock pin = \"clk\") is 9.125 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.334 ns + Longest pin register " "Info: + Longest pin to register delay is 12.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns wr 1 PIN PIN_79 24 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_79; Fanout = 24; PIN Node = 'wr'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 160 -40 128 176 "wr" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.138 ns) + CELL(0.590 ns) 9.203 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|valid_wreq~26 2 COMB LC_X12_Y16_N8 25 " "Info: 2: + IC(7.138 ns) + CELL(0.590 ns) = 9.203 ns; Loc. = LC_X12_Y16_N8; Fanout = 25; COMB Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|valid_wreq~26'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.728 ns" { wr lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 } "NODE_NAME" } } { "db/a_dpfifo_ee21.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/a_dpfifo_ee21.tdf" 73 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.442 ns) 10.931 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|_~66 3 COMB LC_X15_Y16_N8 2 " "Info: 3: + IC(1.286 ns) + CELL(0.442 ns) = 10.931 ns; Loc. = LC_X15_Y16_N8; Fanout = 2; COMB Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|_~66'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.728 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 } "NODE_NAME" } } { "db/scfifo_7821.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/scfifo_7821.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.094 ns) + CELL(0.309 ns) 12.334 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff 4 REG LC_X13_Y16_N7 21 " "Info: 4: + IC(1.094 ns) + CELL(0.309 ns) = 12.334 ns; Loc. = LC_X13_Y16_N7; Fanout = 21; REG Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.403 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_ee21.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/a_dpfifo_ee21.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.816 ns ( 22.83 % ) " "Info: Total cell delay = 2.816 ns ( 22.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.518 ns ( 77.17 % ) " "Info: Total interconnect delay = 9.518 ns ( 77.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.334 ns" { wr lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.334 ns" { wr {} wr~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff {} } { 0.000ns 0.000ns 7.138ns 1.286ns 1.094ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/a_dpfifo_ee21.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/a_dpfifo_ee21.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.246 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff 2 REG LC_X13_Y16_N7 21 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X13_Y16_N7; Fanout = 21; REG Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|empty_dff'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "db/a_dpfifo_ee21.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/a_dpfifo_ee21.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.334 ns" { wr lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.334 ns" { wr {} wr~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|_~66 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff {} } { 0.000ns 0.000ns 7.138ns 1.286ns 1.094ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[0\] lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\] 10.577 ns memory " "Info: tco from clock \"clk\" to destination pin \"q\[0\]\" through memory \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\]\" is 10.577 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.238 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 3.238 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.703 ns) 3.238 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\] 2 MEM M4K_X19_Y16 1 " "Info: 2: + IC(1.066 ns) + CELL(0.703 ns) = 3.238 ns; Loc. = M4K_X19_Y16; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.769 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.172 ns ( 67.08 % ) " "Info: Total cell delay = 2.172 ns ( 67.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.92 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.238 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.238 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.703ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.689 ns + Longest memory pin " "Info: + Longest memory to pin delay is 6.689 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\] 1 MEM M4K_X19_Y16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X19_Y16; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|q_b\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 35 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.461 ns) + CELL(2.124 ns) 6.689 ns q\[0\] 2 PIN PIN_144 0 " "Info: 2: + IC(4.461 ns) + CELL(2.124 ns) = 6.689 ns; Loc. = PIN_144; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.585 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] q[0] } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 136 400 576 152 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.228 ns ( 33.31 % ) " "Info: Total cell delay = 2.228 ns ( 33.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.461 ns ( 66.69 % ) " "Info: Total interconnect delay = 4.461 ns ( 66.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.689 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] q[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.689 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] {} q[0] {} } { 0.000ns 4.461ns } { 0.104ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.238 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.238 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.703ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.689 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] q[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.689 ns" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0] {} q[0] {} } { 0.000ns 4.461ns } { 0.104ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg4 D\[3\] clk -4.700 ns memory " "Info: th for memory \"lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg4\" (data pin = \"D\[3\]\", clock pin = \"clk\") is -4.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.257 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to destination memory is 3.257 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 77; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 200 -40 128 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.722 ns) 3.257 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg4 2 MEM M4K_X19_Y16 1 " "Info: 2: + IC(1.066 ns) + CELL(0.722 ns) = 3.257 ns; Loc. = M4K_X19_Y16; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.788 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 67.27 % ) " "Info: Total cell delay = 2.191 ns ( 67.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.73 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.257 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.257 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.055 ns + " "Info: + Micro hold delay of destination is 0.055 ns" {  } { { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.012 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 8.012 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns D\[3\] 1 PIN PIN_213 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_213; Fanout = 1; PIN Node = 'D\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[3] } "NODE_NAME" } } { "fifo.bdf" "" { Schematic "C:/Documents and Settings/Administrator/fifo/fifo.bdf" { { 136 -40 128 152 "D\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.181 ns) + CELL(0.356 ns) 8.012 ns lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg4 2 MEM M4K_X19_Y16 1 " "Info: 2: + IC(6.181 ns) + CELL(0.356 ns) = 8.012 ns; Loc. = M4K_X19_Y16; Fanout = 1; MEM Node = 'lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7821:auto_generated\|a_dpfifo_ee21:dpfifo\|altsyncram_joa1:FIFOram\|ram_block1a7~porta_datain_reg4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.537 ns" { D[3] lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 } "NODE_NAME" } } { "db/altsyncram_joa1.tdf" "" { Text "C:/Documents and Settings/Administrator/fifo/db/altsyncram_joa1.tdf" 256 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.831 ns ( 22.85 % ) " "Info: Total cell delay = 1.831 ns ( 22.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.181 ns ( 77.15 % ) " "Info: Total interconnect delay = 6.181 ns ( 77.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.012 ns" { D[3] lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.012 ns" { D[3] {} D[3]~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 {} } { 0.000ns 0.000ns 6.181ns } { 0.000ns 1.475ns 0.356ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.257 ns" { clk lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.257 ns" { clk {} clk~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.722ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.012 ns" { D[3] lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.012 ns" { D[3] {} D[3]~out0 {} lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg4 {} } { 0.000ns 0.000ns 6.181ns } { 0.000ns 1.475ns 0.356ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}