scfifo_7821.tdf

先进先出存储电路fifo

--scfifo ADD_RAM_OUTPUT_REGISTER="ON" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=8 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr clock data q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 7.2 cbx_altdpram 2007:04:25:14:55:30:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_fifo_common 2007:04:09:14:30:26:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_counter 2007:08:07:01:40:08:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_scfifo 2007:04:06:15:45:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


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FUNCTION a_dpfifo_ee21 (aclr, clock, data[7..0], rreq, sclr, wreq)
RETURNS ( q[7..0], usedw[7..0]);

--synthesis_resources = lut 47 M4K 1 
SUBDESIGN scfifo_7821
( 
	aclr	:	input;
	clock	:	input;
	data[7..0]	:	input;
	q[7..0]	:	output;
	rdreq	:	input;
	usedw[7..0]	:	output;
	wrreq	:	input;
) 
VARIABLE 
	dpfifo : a_dpfifo_ee21;
	sclr	: NODE;

BEGIN 
	dpfifo.aclr = aclr;
	dpfifo.clock = clock;
	dpfifo.data[] = data[];
	dpfifo.rreq = rdreq;
	dpfifo.sclr = sclr;
	dpfifo.wreq = wrreq;
	q[] = dpfifo.q[];
	sclr = GND;
	usedw[] = dpfifo.usedw[];
END;
--VALID FILE