fifo.sim.rpt

先进先出存储电路fifo

; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------------------------------------------------------------------------------------------------------------------+
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      55.77 % ;
; Total nodes checked                                 ; 76           ;
; Total output ports checked                          ; 104          ;
; Total output ports with complete 1/0-value coverage ; 58           ;
; Total output ports with no 1/0-value coverage       ; 36           ;
; Total output ports with no 1-value coverage         ; 40           ;
; Total output ports with no 0-value coverage         ; 42           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                          ; Output Port Name                                                                                                                             ; Output Port Type ;
+------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7  ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[2]                  ; portbdataout5    ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7  ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[1]                  ; portbdataout6    ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7  ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0]                  ; portbdataout7    ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella4 ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella4~COUT      ; cout             ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella3 ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella3~COUT      ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella3 ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella3~COUTCOUT1 ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella2 ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella2~COUT      ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella2 ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella2~COUTCOUT1 ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella1 ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella1~COUT      ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella1 ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella1~COUTCOUT1 ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella0 ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella0~COUT      ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella0 ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_bc7:usedw_counter|counter_cella0~COUTCOUT1 ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella0        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|safe_q[0]                       ; regout           ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella0        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella0~COUT             ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella0        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella0~COUTCOUT1        ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella1        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|safe_q[1]                       ; regout           ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella1        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella1~COUT             ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella1        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella1~COUTCOUT1        ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella2        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|safe_q[2]                       ; regout           ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella2        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella2~COUT             ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella2        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella2~COUTCOUT1        ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella3        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|safe_q[3]                       ; regout           ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella3        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella3~COUT             ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella3        ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_vbb:wr_ptr|counter_cella3~COUTCOUT1        ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella0    ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella0~COUT         ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella0    ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella0~COUTCOUT1    ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella1    ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella1~COUT         ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella1    ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella1~COUTCOUT1    ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella2    ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella2~COUT         ; cout0            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella2    ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|cntr_ubb:rd_ptr_msb|counter_cella2~COUTCOUT1    ; cout1            ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff                             ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff                                       ; regout           ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_rreq                            ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_rreq                                      ; combout          ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|low_addressa[0]                       ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|ram_read_address[0]~353                         ; combout          ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|low_addressa[1]                       ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|ram_read_address[1]~354                         ; combout          ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|low_addressa[2]                       ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|ram_read_address[2]~355                         ; combout          ;
; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|low_addressa[3]                       ; |fifo|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|ram_read_address[3]~356                         ; combout          ;