fifo.fit.rpt

先进先出存储电路fifo

; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                   ; Care                           ; Care                           ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Administrator/fifo/fifo.pin.


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                                      ;
+---------------------------------------------+------------------------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                                ;
+---------------------------------------------+------------------------------------------------------------------------------------------------------+
; Total logic elements                        ; 48 / 12,060 ( < 1 % )                                                                                ;
;     -- Combinational with no register       ; 12                                                                                                   ;
;     -- Register only                        ; 0                                                                                                    ;
;     -- Combinational with a register        ; 36                                                                                                   ;
;                                             ;                                                                                                      ;
; Logic element usage by number of LUT inputs ;                                                                                                      ;
;     -- 4 input functions                    ; 18                                                                                                   ;
;     -- 3 input functions                    ; 22                                                                                                   ;
;     -- 2 input functions                    ; 6                                                                                                    ;
;     -- 1 input functions                    ; 2                                                                                                    ;
;     -- 0 input functions                    ; 0                                                                                                    ;
;                                             ;                                                                                                      ;
; Logic elements by mode                      ;                                                                                                      ;
;     -- normal mode                          ; 28                                                                                                   ;
;     -- arithmetic mode                      ; 20                                                                                                   ;
;     -- qfbk mode                            ; 8                                                                                                    ;
;     -- register cascade mode                ; 0                                                                                                    ;
;     -- synchronous clear/load mode          ; 0                                                                                                    ;
;     -- asynchronous clear/load mode         ; 36                                                                                                   ;
;                                             ;                                                                                                      ;
; Total registers                             ; 36 / 12,567 ( < 1 % )                                                                                ;
; Total LABs                                  ; 6 / 1,206 ( < 1 % )                                                                                  ;
; Logic elements in carry chains              ; 23                                                                                                   ;
; User inserted logic elements                ; 0                                                                                                    ;
; Virtual pins                                ; 0                                                                                                    ;
; I/O pins                                    ; 27 / 173 ( 16 % )                                                                                    ;
;     -- Clock pins                           ; 0 / 2 ( 0 % )                                                                                        ;
; Global signals                              ; 2                                                                                                    ;
; M4Ks                                        ; 1 / 52 ( 2 % )                                                                                       ;
; Total memory bits                           ; 2,048 / 239,616 ( < 1 % )                                                                            ;
; Total RAM block bits                        ; 4,608 / 239,616 ( 2 % )                                                                              ;
; PLLs                                        ; 0 / 2 ( 0 % )                                                                                        ;
; Global clocks                               ; 2 / 8 ( 25 % )                                                                                       ;
; Average interconnect usage                  ; 0%                                                                                                   ;
; Peak interconnect usage                     ; 1%                                                                                                   ;
; Maximum fan-out node                        ; clk                                                                                                  ;
; Maximum fan-out                             ; 37                                                                                                   ;
; Highest non-global fan-out signal           ; lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|valid_wreq~26 ;
; Highest non-global fan-out                  ; 18                                                                                                   ;
; Total fan-out                               ; 274                                                                                                  ;
; Average fan-out                             ; 3.51                                                                                                 ;
+---------------------------------------------+------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;