fifo.tan.rpt

来自「先进先出存储电路fifo」· RPT 代码 · 共 201 行 · 第 1/5 页

+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                           ; To                                                                                                                                            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 7.238 ns                         ; wr                                                                                                                                             ; lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|empty_dff                                              ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 16.453 ns                        ; lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[0]                          ; q[0]                                                                                                                                          ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -2.328 ns                        ; D[7]                                                                                                                                           ; lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~porta_datain_reg0 ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 196.97 MHz ( period = 5.077 ns ) ; lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|ram_block1a7~portb_address_reg7 ; lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7821:auto_generated|a_dpfifo_ee21:dpfifo|altsyncram_joa1:FIFOram|q_b[6]                         ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                                                                ;                                                                                                                                               ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;