fifo1.v.bak

异步FIFO的设计 包括testbench 已调试成功

module fifo1(data_out,empty,full,data_in,clk_read,read,clk_write,write, rst);
    parameter    DATA_WIDTH    = 8;
    parameter    ADDRESS_WIDTH = 6;
    parameter    FIFO_DEPTH    = 64;
    
    output   [DATA_WIDTH-1:0]        data_out; 
    output                           empty;
    output                           full; 
    input    [DATA_WIDTH-1:0]        data_in;
    input                            clk_read;
    input                            read;        
    input                            clk_write;
    input                            write;
    input                            rst ;

    reg  [DATA_WIDTH-1:0]        data_out;
    wire                         empty;
    wire                         full;

    /////Internal connections & variables//////
    reg   [DATA_WIDTH-1:0]              mem [FIFO_DEPTH-1:0];
    wire  [ADDRESS_WIDTH:0]             write_ptr;
    wire  [ADDRESS_WIDTH:0]             read_ptr;
    wire  [ADDRESS_WIDTH-1:0]           write_addr;
    wire  [ADDRESS_WIDTH-1:0]           read_addr;
    wire                                write_enable;
    wire                                read_enable;
    

    //mem logic
    always @(posedge clk_read) begin
        if (read_enable) begin
            data_out <= mem[read_addr];
        end
    end
 
    always @(posedge clk_write or negedge rst) begin
        if (!rst)
            mem[write_addr] <= 0;
            
        else 
        if (write_enable) begin
            mem[write_addr] <= data_in;
        end  
    end
 
    //Enable
    assign write_enable = write & ~full;
    assign read_enable  = read  & ~empty;
           
    //Addreses change to Gray code
    GrayCounter_2 GrayCounter_write
       (write_ptr,
        write_addr,       //get out a binary  value
        write_enable, 
        rst,
        clk_write);
       
    GrayCounter_2 GrayCounter_read
       (read_ptr, 
        read_addr,       //get out a binary value
        read_enable,
        rst,
        clk_read);
    
    //writing full  
    assign full = (write_ptr[ADDRESS_WIDTH:ADDRESS_WIDTH-1] == 
                  ~read_ptr[ADDRESS_WIDTH:ADDRESS_WIDTH-1]) &&
                  (write_ptr[ADDRESS_WIDTH-2:0] == 
                   read_ptr[ADDRESS_WIDTH-2:0]);
                   
    //reading empty
    assign empty = (write_ptr == read_ptr);
    
    
endmodule



module GrayCounter_2(
    gray_out,
    bin_addr,
    enable,
    rst,
    clk
    );
    
  parameter   COUNTER_WIDTH = 7 ;
   
  output   [COUNTER_WIDTH-1:0]    gray_out;  //'Gray' code count output.
  output   [COUNTER_WIDTH-2:0]    bin_addr;
    
  input                           enable;    //Count enable.
  input                           rst;       //Count reset.
  input                           clk; 

  reg      [COUNTER_WIDTH-1:0]    gray_out;
  reg      [COUNTER_WIDTH-1:0]    bin;

  assign  bin_addr = bin[COUNTER_WIDTH-2:0];
 
  always @ (posedge clk or negedge rst) begin
     if (!rst) begin
         bin      <= 1;   
         gray_out <= 0;      
     end
     else if (enable) begin
         bin   <= bin + 1;
         gray_out <= (bin>>1)^bin;
     end
   end  //end always @(posedge clk or negedge rst)
    
endmodule