_primary.vhd

来自「异步FIFO的设计 包括testbench 已调试成功」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity GrayCounter_2 is
    generic(
        COUNTER_WIDTH   : integer := 7
    );
    port(
        gray_out        : out    vl_logic_vector;
        bin_addr        : out    vl_logic_vector;
        enable          : in     vl_logic;
        rst             : in     vl_logic;
        clk             : in     vl_logic
    );
end GrayCounter_2;