_primary.vhd

来自「异步FIFO的设计 包括testbench 已调试成功」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity fifo1 is
    generic(
        DATA_WIDTH      : integer := 8;
        ADDRESS_WIDTH   : integer := 6;
        FIFO_DEPTH      : integer := 64
    );
    port(
        data_out        : out    vl_logic_vector;
        empty           : out    vl_logic;
        full            : out    vl_logic;
        data_in         : in     vl_logic_vector;
        clk_read        : in     vl_logic;
        read            : in     vl_logic;
        clk_write       : in     vl_logic;
        write           : in     vl_logic;
        rst             : in     vl_logic
    );
end fifo1;