jiaotongdeng.map.rpt

这程序是利用状态机来控制交通灯verilog码

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+-----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+
; Compilation Hierarchy Node  ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                  ; Library Name ;
+-----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+
; |jiaotongdeng               ; 146 (0)           ; 84 (0)       ; 0           ; 0            ; 0       ; 0         ; 24   ; 0            ; |jiaotongdeng                        ; work         ;
;    |int_div2:inst1|         ; 51 (51)           ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |jiaotongdeng|int_div2:inst1         ; work         ;
;    |int_div:inst|           ; 54 (54)           ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |jiaotongdeng|int_div:inst           ; work         ;
;    |jiaotongdeng_con:inst3| ; 29 (29)           ; 17 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |jiaotongdeng|jiaotongdeng_con:inst3 ; work         ;
;    |seg_7:inst4|            ; 12 (12)           ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |jiaotongdeng|seg_7:inst4            ; work         ;
+-----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+---------------------------------------------------------+
; State Machine - |jiaotongdeng|jiaotongdeng_con:inst3|CS ;
+--------+--------+--------+--------+---------------------+
; Name   ; CS.st4 ; CS.st3 ; CS.st2 ; CS.st1              ;
+--------+--------+--------+--------+---------------------+
; CS.st1 ; 0      ; 0      ; 0      ; 0                   ;
; CS.st2 ; 0      ; 0      ; 1      ; 1                   ;
; CS.st3 ; 0      ; 1      ; 0      ; 1                   ;
; CS.st4 ; 1      ; 0      ; 0      ; 1                   ;
+--------+--------+--------+--------+---------------------+


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; jiaotongdeng_con:inst3|gb             ; Merged with jiaotongdeng_con:inst3|ga  ;
; jiaotongdeng_con:inst3|CS~19          ; Lost fanout                            ;
; jiaotongdeng_con:inst3|CS~20          ; Lost fanout                            ;
; seg_7:inst4|a[1]                      ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 4 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 84    ;
; Number of registers using Synchronous Clear  ; 64    ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |jiaotongdeng|jiaotongdeng_con:inst3|qh[3] ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |jiaotongdeng|jiaotongdeng_con:inst3|ql[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: jiaotongdeng_con:inst3 ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; st1            ; 00    ; Unsigned Binary                            ;
; st2            ; 01    ; Unsigned Binary                            ;
; st3            ; 10    ; Unsigned Binary                            ;
; st4            ; 11    ; Unsigned Binary                            ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: int_div:inst ;
+----------------+----------+-------------------------------+
; Parameter Name ; Value    ; Type                          ;
+----------------+----------+-------------------------------+
; F_DIV          ; 48000000 ; Untyped                       ;
; F_DIV_WIDTH    ; 32       ; Untyped                       ;
+----------------+----------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: int_div2:inst1 ;
+----------------+--------+-----------------------------------+
; Parameter Name ; Value  ; Type                              ;
+----------------+--------+-----------------------------------+
; F_DIV          ; 100000 ; Untyped                           ;
; F_DIV_WIDTH    ; 32     ; Untyped                           ;
+----------------+--------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Thu Jan 15 19:59:21 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng
Warning: Can't analyze file -- file C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.v is missing
Warning: Can't analyze file -- file C:/Documents and Settings/Administrator/桌面/jiaotongdeng/Block1.bdf is missing
Info: Found 1 design units, including 1 entities, in source file int_div.v
    Info: Found entity 1: int_div
Info: Found 1 design units, including 1 entities, in source file int_div2.v
    Info: Found entity 1: int_div2
Info: Found 1 design units, including 1 entities, in source file jiaotongdeng_con.v
    Info: Found entity 1: jiaotongdeng_con
Info: Found 1 design units, including 1 entities, in source file seg_7.v
    Info: Found entity 1: seg_7
Info: Found 1 design units, including 1 entities, in source file jiaotongdeng.bdf
    Info: Found entity 1: jiaotongdeng
Info: Elaborating entity "jiaotongdeng" for the top level hierarchy
Info: Elaborating entity "jiaotongdeng_con" for hierarchy "jiaotongdeng_con:inst3"
Warning (10235): Verilog HDL Always Construct warning at jiaotongdeng_con.v(55): variable "CS" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(106): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(110): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(133): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(158): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(162): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(186): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "int_div" for hierarchy "int_div:inst"
Info: Elaborating entity "seg_7" for hierarchy "seg_7:inst4"
Warning (10230): Verilog HDL assignment warning at seg_7.v(17): truncated value with size 32 to match size of target (2)
Warning (10235): Verilog HDL Always Construct warning at seg_7.v(23): variable "qh" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at seg_7.v(24): variable "ql" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10270): Verilog HDL Case Statement warning at seg_7.v(22): incomplete case statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at seg_7.v(20): inferring latch(es) for variable "scan", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at seg_7.v(20): inferring latch(es) for variable "temp", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "temp[0]" at seg_7.v(20)
Info (10041): Inferred latch for "temp[1]" at seg_7.v(20)
Info (10041): Inferred latch for "temp[2]" at seg_7.v(20)
Info (10041): Inferred latch for "temp[3]" at seg_7.v(20)
Info (10041): Inferred latch for "scan[0]" at seg_7.v(20)
Info (10041): Inferred latch for "scan[1]" at seg_7.v(20)
Info (10041): Inferred latch for "scan[2]" at seg_7.v(20)
Info (10041): Inferred latch for "scan[3]" at seg_7.v(20)
Info (10041): Inferred latch for "scan[4]" at seg_7.v(20)
Info (10041): Inferred latch for "scan[5]" at seg_7.v(20)
Info (10041): Inferred latch for "scan[6]" at seg_7.v(20)
Info (10041): Inferred latch for "scan[7]" at seg_7.v(20)
Info: Elaborating entity "int_div2" for hierarchy "int_div2:inst1"
Warning: LATCH primitive "seg_7:inst4|scan[7]" is permanently enabled
Warning: LATCH primitive "seg_7:inst4|scan[6]" is permanently enabled
Warning: LATCH primitive "seg_7:inst4|temp[0]" is permanently enabled
Warning: LATCH primitive "seg_7:inst4|temp[1]" is permanently enabled
Warning: LATCH primitive "seg_7:inst4|temp[2]" is permanently enabled
Warning: LATCH primitive "seg_7:inst4|temp[3]" is permanently enabled
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "scan[5]" is stuck at VCC
    Warning (13410): Pin "scan[4]" is stuck at VCC
    Warning (13410): Pin "scan[3]" is stuck at VCC
    Warning (13410): Pin "scan[2]" is stuck at VCC
    Warning (13410): Pin "scan[1]" is stuck at VCC
    Warning (13410): Pin "scan[0]" is stuck at VCC
    Warning (13410): Pin "seg[7]" is stuck at VCC
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
    Info: Register "jiaotongdeng_con:inst3|CS~19" lost all its fanouts during netlist optimizations.
    Info: Register "jiaotongdeng_con:inst3|CS~20" lost all its fanouts during netlist optimizations.
Info: Implemented 174 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 22 output pins
    Info: Implemented 150 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings
    Info: Peak virtual memory: 167 megabytes
    Info: Processing ended: Thu Jan 15 19:59:25 2009
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:02