prev_cmp_jiaotongdeng.qmsg

这程序是利用状态机来控制交通灯verilog码

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "temp\[1\] seg_7.v(20) " "Info (10041): Inferred latch for \"temp\[1\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "temp\[2\] seg_7.v(20) " "Info (10041): Inferred latch for \"temp\[2\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "temp\[3\] seg_7.v(20) " "Info (10041): Inferred latch for \"temp\[3\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[0\] seg_7.v(20) " "Info (10041): Inferred latch for \"scan\[0\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[1\] seg_7.v(20) " "Info (10041): Inferred latch for \"scan\[1\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[2\] seg_7.v(20) " "Info (10041): Inferred latch for \"scan\[2\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[3\] seg_7.v(20) " "Info (10041): Inferred latch for \"scan\[3\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[4\] seg_7.v(20) " "Info (10041): Inferred latch for \"scan\[4\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[5\] seg_7.v(20) " "Info (10041): Inferred latch for \"scan\[5\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[6\] seg_7.v(20) " "Info (10041): Inferred latch for \"scan\[6\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[7\] seg_7.v(20) " "Info (10041): Inferred latch for \"scan\[7\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "int_div2 int_div2:inst1 " "Info: Elaborating entity \"int_div2\" for hierarchy \"int_div2:inst1\"" {  } { { "jiaotongdeng.bdf" "inst1" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 56 288 400 152 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "jiaotongdeng_con:inst3\|gb jiaotongdeng_con:inst3\|ga " "Info: Duplicate register \"jiaotongdeng_con:inst3\|gb\" merged to single register \"jiaotongdeng_con:inst3\|ga\", power-up level changed" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 5 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS 4 " "Info: State machine \"\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS\" contains 4 states" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|jiaotongdeng\|jiaotongdeng_con:inst3\|CS " "Info: Selected Auto state machine encoding method for state machine \"\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS\"" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS " "Info: Encoding result for state machine \"\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiaotongdeng_con:inst3\|CS.st4 " "Info: Encoded state bit \"jiaotongdeng_con:inst3\|CS.st4\"" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiaotongdeng_con:inst3\|CS.st3 " "Info: Encoded state bit \"jiaotongdeng_con:inst3\|CS.st3\"" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiaotongdeng_con:inst3\|CS.st2 " "Info: Encoded state bit \"jiaotongdeng_con:inst3\|CS.st2\"" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiaotongdeng_con:inst3\|CS.st1 " "Info: Encoded state bit \"jiaotongdeng_con:inst3\|CS.st1\"" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS.st1 0000 " "Info: State \"\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS.st1\" uses code string \"0000\"" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS.st2 0011 " "Info: State \"\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS.st2\" uses code string \"0011\"" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS.st3 0101 " "Info: State \"\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS.st3\" uses code string \"0101\"" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS.st4 1001 " "Info: State \"\|jiaotongdeng\|jiaotongdeng_con:inst3\|CS.st4\" uses code string \"1001\"" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "seg_7:inst4\|a\[1\] data_in GND " "Warning (14130): Reduced register \"seg_7:inst4\|a\[1\]\" with stuck data_in port to stuck value GND" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 12 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_7:inst4\|scan\[7\] " "Warning: LATCH primitive \"seg_7:inst4\|scan\[7\]\" is permanently enabled" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_7:inst4\|scan\[6\] " "Warning: LATCH primitive \"seg_7:inst4\|scan\[6\]\" is permanently enabled" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_7:inst4\|temp\[0\] " "Warning: LATCH primitive \"seg_7:inst4\|temp\[0\]\" is permanently enabled" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_7:inst4\|temp\[1\] " "Warning: LATCH primitive \"seg_7:inst4\|temp\[1\]\" is permanently enabled" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_7:inst4\|temp\[2\] " "Warning: LATCH primitive \"seg_7:inst4\|temp\[2\]\" is permanently enabled" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_7:inst4\|temp\[3\] " "Warning: LATCH primitive \"seg_7:inst4\|temp\[3\]\" is permanently enabled" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[5\] VCC " "Warning (13410): Pin \"scan\[5\]\" stuck at VCC" {  } { { "jiaotongdeng.bdf" "" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 240 808 984 256 "scan\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[4\] VCC " "Warning (13410): Pin \"scan\[4\]\" stuck at VCC" {  } { { "jiaotongdeng.bdf" "" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 240 808 984 256 "scan\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[3\] VCC " "Warning (13410): Pin \"scan\[3\]\" stuck at VCC" {  } { { "jiaotongdeng.bdf" "" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 240 808 984 256 "scan\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[2\] VCC " "Warning (13410): Pin \"scan\[2\]\" stuck at VCC" {  } { { "jiaotongdeng.bdf" "" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 240 808 984 256 "scan\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[1\] VCC " "Warning (13410): Pin \"scan\[1\]\" stuck at VCC" {  } { { "jiaotongdeng.bdf" "" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 240 808 984 256 "scan\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[0\] VCC " "Warning (13410): Pin \"scan\[0\]\" stuck at VCC" {  } { { "jiaotongdeng.bdf" "" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 240 808 984 256 "scan\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[7\] VCC " "Warning (13410): Pin \"seg\[7\]\" stuck at VCC" {  } { { "jiaotongdeng.bdf" "" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 256 808 984 272 "seg\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "jiaotongdeng_con:inst3\|CS~19 " "Info: Register \"jiaotongdeng_con:inst3\|CS~19\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "jiaotongdeng_con:inst3\|CS~20 " "Info: Register \"jiaotongdeng_con:inst3\|CS~20\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "174 " "Info: Implemented 174 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "22 " "Info: Implemented 22 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "150 " "Info: Implemented 150 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 29 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Allocated 144 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 14 16:52:31 2009 " "Info: Processing ended: Wed Jan 14 16:52:31 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}