📄 jiaotongdeng.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "int_div2:inst1\|clk_p_r " "Info: Detected ripple clock \"int_div2:inst1\|clk_p_r\" as buffer" { } { { "int_div2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div2.v" 50 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "int_div2:inst1\|clk_p_r" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "int_div:inst\|clk_p_r " "Info: Detected ripple clock \"int_div:inst\|clk_p_r\" as buffer" { } { { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "int_div:inst\|clk_p_r" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register int_div:inst\|count_p\[28\] register int_div:inst\|count_p\[25\] 130.74 MHz 7.649 ns Internal " "Info: Clock \"clock\" has Internal fmax of 130.74 MHz between source register \"int_div:inst\|count_p\[28\]\" and destination register \"int_div:inst\|count_p\[25\]\" (period= 7.649 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.385 ns + Longest register register " "Info: + Longest register to register delay is 7.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|count_p\[28\] 1 REG LCFF_X15_Y2_N25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y2_N25; Fanout = 3; REG Node = 'int_div:inst\|count_p\[28\]'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_div:inst|count_p[28] } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.243 ns) + CELL(0.534 ns) 2.777 ns int_div:inst\|LessThan0~783 2 COMB LCCOMB_X25_Y4_N0 1 " "Info: 2: + IC(2.243 ns) + CELL(0.534 ns) = 2.777 ns; Loc. = LCCOMB_X25_Y4_N0; Fanout = 1; COMB Node = 'int_div:inst\|LessThan0~783'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { int_div:inst|count_p[28] int_div:inst|LessThan0~783 } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.353 ns) + CELL(0.206 ns) 3.336 ns int_div:inst\|LessThan0~784 3 COMB LCCOMB_X25_Y4_N10 1 " "Info: 3: + IC(0.353 ns) + CELL(0.206 ns) = 3.336 ns; Loc. = LCCOMB_X25_Y4_N10; Fanout = 1; COMB Node = 'int_div:inst\|LessThan0~784'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.559 ns" { int_div:inst|LessThan0~783 int_div:inst|LessThan0~784 } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.142 ns) + CELL(0.206 ns) 5.684 ns int_div:inst\|LessThan0~791 4 COMB LCCOMB_X14_Y3_N12 33 " "Info: 4: + IC(2.142 ns) + CELL(0.206 ns) = 5.684 ns; Loc. = LCCOMB_X14_Y3_N12; Fanout = 33; COMB Node = 'int_div:inst\|LessThan0~791'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { int_div:inst|LessThan0~784 int_div:inst|LessThan0~791 } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.660 ns) 7.385 ns int_div:inst\|count_p\[25\] 5 REG LCFF_X15_Y2_N19 4 " "Info: 5: + IC(1.041 ns) + CELL(0.660 ns) = 7.385 ns; Loc. = LCFF_X15_Y2_N19; Fanout = 4; REG Node = 'int_div:inst\|count_p\[25\]'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.701 ns" { int_div:inst|LessThan0~791 int_div:inst|count_p[25] } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.606 ns ( 21.75 % ) " "Info: Total cell delay = 1.606 ns ( 21.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.779 ns ( 78.25 % ) " "Info: Total interconnect delay = 5.779 ns ( 78.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.385 ns" { int_div:inst|count_p[28] int_div:inst|LessThan0~783 int_div:inst|LessThan0~784 int_div:inst|LessThan0~791 int_div:inst|count_p[25] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.385 ns" { int_div:inst|count_p[28] {} int_div:inst|LessThan0~783 {} int_div:inst|LessThan0~784 {} int_div:inst|LessThan0~791 {} int_div:inst|count_p[25] {} } { 0.000ns 2.243ns 0.353ns 2.142ns 1.041ns } { 0.000ns 0.534ns 0.206ns 0.206ns 0.660ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.784 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'clock'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 248 -64 104 264 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clock~clkctrl 2 COMB CLKCTRL_G2 64 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clock~clkctrl'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clock clock~clkctrl } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 248 -64 104 264 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.835 ns) + CELL(0.666 ns) 2.784 ns int_div:inst\|count_p\[25\] 3 REG LCFF_X15_Y2_N19 4 " "Info: 3: + IC(0.835 ns) + CELL(0.666 ns) = 2.784 ns; Loc. = LCFF_X15_Y2_N19; Fanout = 4; REG Node = 'int_div:inst\|count_p\[25\]'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { clock~clkctrl int_div:inst|count_p[25] } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.87 % ) " "Info: Total cell delay = 1.806 ns ( 64.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.978 ns ( 35.13 % ) " "Info: Total interconnect delay = 0.978 ns ( 35.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clock clock~clkctrl int_div:inst|count_p[25] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst|count_p[25] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.784 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'clock'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 248 -64 104 264 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clock~clkctrl 2 COMB CLKCTRL_G2 64 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clock~clkctrl'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clock clock~clkctrl } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 248 -64 104 264 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.835 ns) + CELL(0.666 ns) 2.784 ns int_div:inst\|count_p\[28\] 3 REG LCFF_X15_Y2_N25 3 " "Info: 3: + IC(0.835 ns) + CELL(0.666 ns) = 2.784 ns; Loc. = LCFF_X15_Y2_N25; Fanout = 3; REG Node = 'int_div:inst\|count_p\[28\]'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { clock~clkctrl int_div:inst|count_p[28] } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.87 % ) " "Info: Total cell delay = 1.806 ns ( 64.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.978 ns ( 35.13 % ) " "Info: Total interconnect delay = 0.978 ns ( 35.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clock clock~clkctrl int_div:inst|count_p[28] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst|count_p[28] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clock clock~clkctrl int_div:inst|count_p[25] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst|count_p[25] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clock clock~clkctrl int_div:inst|count_p[28] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst|count_p[28] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.385 ns" { int_div:inst|count_p[28] int_div:inst|LessThan0~783 int_div:inst|LessThan0~784 int_div:inst|LessThan0~791 int_div:inst|count_p[25] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.385 ns" { int_div:inst|count_p[28] {} int_div:inst|LessThan0~783 {} int_div:inst|LessThan0~784 {} int_div:inst|LessThan0~791 {} int_div:inst|count_p[25] {} } { 0.000ns 2.243ns 0.353ns 2.142ns 1.041ns } { 0.000ns 0.534ns 0.206ns 0.206ns 0.660ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clock clock~clkctrl int_div:inst|count_p[25] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst|count_p[25] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clock clock~clkctrl int_div:inst|count_p[28] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst|count_p[28] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "jiaotongdeng_con:inst3\|CS.st4 clr clock 1.160 ns register " "Info: tsu for register \"jiaotongdeng_con:inst3\|CS.st4\" (data pin = \"clr\", clock pin = \"clock\") is 1.160 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.575 ns + Longest pin register " "Info: + Longest pin to register delay is 8.575 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns clr 1 PIN PIN_74 4 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_74; Fanout = 4; PIN Node = 'clr'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 352 48 216 368 "clr" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.914 ns) + CELL(0.589 ns) 8.467 ns jiaotongdeng_con:inst3\|CS~210 2 COMB LCCOMB_X18_Y8_N2 1 " "Info: 2: + IC(6.914 ns) + CELL(0.589 ns) = 8.467 ns; Loc. = LCCOMB_X18_Y8_N2; Fanout = 1; COMB Node = 'jiaotongdeng_con:inst3\|CS~210'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.503 ns" { clr jiaotongdeng_con:inst3|CS~210 } "NODE_NAME" } } { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.575 ns jiaotongdeng_con:inst3\|CS.st4 3 REG LCFF_X18_Y8_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.575 ns; Loc. = LCFF_X18_Y8_N3; Fanout = 2; REG Node = 'jiaotongdeng_con:inst3\|CS.st4'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { jiaotongdeng_con:inst3|CS~210 jiaotongdeng_con:inst3|CS.st4 } "NODE_NAME" } } { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.661 ns ( 19.37 % ) " "Info: Total cell delay = 1.661 ns ( 19.37 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.914 ns ( 80.63 % ) " "Info: Total interconnect delay = 6.914 ns ( 80.63 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.575 ns" { clr jiaotongdeng_con:inst3|CS~210 jiaotongdeng_con:inst3|CS.st4 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.575 ns" { clr {} clr~combout {} jiaotongdeng_con:inst3|CS~210 {} jiaotongdeng_con:inst3|CS.st4 {} } { 0.000ns 0.000ns 6.914ns 0.000ns } { 0.000ns 0.964ns 0.589ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 7.375 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 7.375 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'clock'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 248 -64 104 264 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.558 ns) + CELL(0.970 ns) 3.668 ns int_div:inst\|clk_p_r 2 REG LCFF_X14_Y3_N25 1 " "Info: 2: + IC(1.558 ns) + CELL(0.970 ns) = 3.668 ns; Loc. = LCFF_X14_Y3_N25; Fanout = 1; REG Node = 'int_div:inst\|clk_p_r'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.528 ns" { clock int_div:inst|clk_p_r } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.201 ns) + CELL(0.000 ns) 5.869 ns int_div:inst\|clk_p_r~clkctrl 3 COMB CLKCTRL_G5 17 " "Info: 3: + IC(2.201 ns) + CELL(0.000 ns) = 5.869 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'int_div:inst\|clk_p_r~clkctrl'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.201 ns" { int_div:inst|clk_p_r int_div:inst|clk_p_r~clkctrl } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.666 ns) 7.375 ns jiaotongdeng_con:inst3\|CS.st4 4 REG LCFF_X18_Y8_N3 2 " "Info: 4: + IC(0.840 ns) + CELL(0.666 ns) = 7.375 ns; Loc. = LCFF_X18_Y8_N3; Fanout = 2; REG Node = 'jiaotongdeng_con:inst3\|CS.st4'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.506 ns" { int_div:inst|clk_p_r~clkctrl jiaotongdeng_con:inst3|CS.st4 } "NODE_NAME" } } { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 37.64 % ) " "Info: Total cell delay = 2.776 ns ( 37.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.599 ns ( 62.36 % ) " "Info: Total interconnect delay = 4.599 ns ( 62.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.375 ns" { clock int_div:inst|clk_p_r int_div:inst|clk_p_r~clkctrl jiaotongdeng_con:inst3|CS.st4 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.375 ns" { clock {} clock~combout {} int_div:inst|clk_p_r {} int_div:inst|clk_p_r~clkctrl {} jiaotongdeng_con:inst3|CS.st4 {} } { 0.000ns 0.000ns 1.558ns 2.201ns 0.840ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.575 ns" { clr jiaotongdeng_con:inst3|CS~210 jiaotongdeng_con:inst3|CS.st4 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.575 ns" { clr {} clr~combout {} jiaotongdeng_con:inst3|CS~210 {} jiaotongdeng_con:inst3|CS.st4 {} } { 0.000ns 0.000ns 6.914ns 0.000ns } { 0.000ns 0.964ns 0.589ns 0.108ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.375 ns" { clock int_div:inst|clk_p_r int_div:inst|clk_p_r~clkctrl jiaotongdeng_con:inst3|CS.st4 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.375 ns" { clock {} clock~combout {} int_div:inst|clk_p_r {} int_div:inst|clk_p_r~clkctrl {} jiaotongdeng_con:inst3|CS.st4 {} } { 0.000ns 0.000ns 1.558ns 2.201ns 0.840ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock seg\[4\] jiaotongdeng_con:inst3\|ql\[3\] 15.639 ns register " "Info: tco from clock \"clock\" to destination pin \"seg\[4\]\" through register \"jiaotongdeng_con:inst3\|ql\[3\]\" is 15.639 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 7.376 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 7.376 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'clock'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 248 -64 104 264 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.558 ns) + CELL(0.970 ns) 3.668 ns int_div:inst\|clk_p_r 2 REG LCFF_X14_Y3_N25 1 " "Info: 2: + IC(1.558 ns) + CELL(0.970 ns) = 3.668 ns; Loc. = LCFF_X14_Y3_N25; Fanout = 1; REG Node = 'int_div:inst\|clk_p_r'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.528 ns" { clock int_div:inst|clk_p_r } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.201 ns) + CELL(0.000 ns) 5.869 ns int_div:inst\|clk_p_r~clkctrl 3 COMB CLKCTRL_G5 17 " "Info: 3: + IC(2.201 ns) + CELL(0.000 ns) = 5.869 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'int_div:inst\|clk_p_r~clkctrl'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.201 ns" { int_div:inst|clk_p_r int_div:inst|clk_p_r~clkctrl } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.841 ns) + CELL(0.666 ns) 7.376 ns jiaotongdeng_con:inst3\|ql\[3\] 4 REG LCFF_X19_Y8_N1 3 " "Info: 4: + IC(0.841 ns) + CELL(0.666 ns) = 7.376 ns; Loc. = LCFF_X19_Y8_N1; Fanout = 3; REG Node = 'jiaotongdeng_con:inst3\|ql\[3\]'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.507 ns" { int_div:inst|clk_p_r~clkctrl jiaotongdeng_con:inst3|ql[3] } "NODE_NAME" } } { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 83 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 37.64 % ) " "Info: Total cell delay = 2.776 ns ( 37.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns ( 62.36 % ) " "Info: Total interconnect delay = 4.600 ns ( 62.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.376 ns" { clock int_div:inst|clk_p_r int_div:inst|clk_p_r~clkctrl jiaotongdeng_con:inst3|ql[3] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.376 ns" { clock {} clock~combout {} int_div:inst|clk_p_r {} int_div:inst|clk_p_r~clkctrl {} jiaotongdeng_con:inst3|ql[3] {} } { 0.000ns 0.000ns 1.558ns 2.201ns 0.841ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 83 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.959 ns + Longest register pin " "Info: + Longest register to pin delay is 7.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiaotongdeng_con:inst3\|ql\[3\] 1 REG LCFF_X19_Y8_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y8_N1; Fanout = 3; REG Node = 'jiaotongdeng_con:inst3\|ql\[3\]'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiaotongdeng_con:inst3|ql[3] } "NODE_NAME" } } { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 83 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.624 ns) 1.712 ns seg_7:inst4\|Selector3~17 2 COMB LCCOMB_X20_Y8_N26 7 " "Info: 2: + IC(1.088 ns) + CELL(0.624 ns) = 1.712 ns; Loc. = LCCOMB_X20_Y8_N26; Fanout = 7; COMB Node = 'seg_7:inst4\|Selector3~17'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.712 ns" { jiaotongdeng_con:inst3|ql[3] seg_7:inst4|Selector3~17 } "NODE_NAME" } } { "seg_7.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/seg_7.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.624 ns) 2.759 ns seg_7:inst4\|WideOr2~23 3 COMB LCCOMB_X20_Y8_N16 1 " "Info: 3: + IC(0.423 ns) + CELL(0.624 ns) = 2.759 ns; Loc. = LCCOMB_X20_Y8_N16; Fanout = 1; COMB Node = 'seg_7:inst4\|WideOr2~23'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.047 ns" { seg_7:inst4|Selector3~17 seg_7:inst4|WideOr2~23 } "NODE_NAME" } } { "seg_7.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/seg_7.v" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.094 ns) + CELL(3.106 ns) 7.959 ns seg\[4\] 4 PIN PIN_113 0 " "Info: 4: + IC(2.094 ns) + CELL(3.106 ns) = 7.959 ns; Loc. = PIN_113; Fanout = 0; PIN Node = 'seg\[4\]'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { seg_7:inst4|WideOr2~23 seg[4] } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 256 808 984 272 "seg\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.354 ns ( 54.71 % ) " "Info: Total cell delay = 4.354 ns ( 54.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.605 ns ( 45.29 % ) " "Info: Total interconnect delay = 3.605 ns ( 45.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.959 ns" { jiaotongdeng_con:inst3|ql[3] seg_7:inst4|Selector3~17 seg_7:inst4|WideOr2~23 seg[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.959 ns" { jiaotongdeng_con:inst3|ql[3] {} seg_7:inst4|Selector3~17 {} seg_7:inst4|WideOr2~23 {} seg[4] {} } { 0.000ns 1.088ns 0.423ns 2.094ns } { 0.000ns 0.624ns 0.624ns 3.106ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.376 ns" { clock int_div:inst|clk_p_r int_div:inst|clk_p_r~clkctrl jiaotongdeng_con:inst3|ql[3] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.376 ns" { clock {} clock~combout {} int_div:inst|clk_p_r {} int_div:inst|clk_p_r~clkctrl {} jiaotongdeng_con:inst3|ql[3] {} } { 0.000ns 0.000ns 1.558ns 2.201ns 0.841ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.959 ns" { jiaotongdeng_con:inst3|ql[3] seg_7:inst4|Selector3~17 seg_7:inst4|WideOr2~23 seg[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.959 ns" { jiaotongdeng_con:inst3|ql[3] {} seg_7:inst4|Selector3~17 {} seg_7:inst4|WideOr2~23 {} seg[4] {} } { 0.000ns 1.088ns 0.423ns 2.094ns } { 0.000ns 0.624ns 0.624ns 3.106ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "jiaotongdeng_con:inst3\|CS.st3 clr clock -0.676 ns register " "Info: th for register \"jiaotongdeng_con:inst3\|CS.st3\" (data pin = \"clr\", clock pin = \"clock\") is -0.676 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 7.375 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 7.375 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'clock'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 248 -64 104 264 "clock" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.558 ns) + CELL(0.970 ns) 3.668 ns int_div:inst\|clk_p_r 2 REG LCFF_X14_Y3_N25 1 " "Info: 2: + IC(1.558 ns) + CELL(0.970 ns) = 3.668 ns; Loc. = LCFF_X14_Y3_N25; Fanout = 1; REG Node = 'int_div:inst\|clk_p_r'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.528 ns" { clock int_div:inst|clk_p_r } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.201 ns) + CELL(0.000 ns) 5.869 ns int_div:inst\|clk_p_r~clkctrl 3 COMB CLKCTRL_G5 17 " "Info: 3: + IC(2.201 ns) + CELL(0.000 ns) = 5.869 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'int_div:inst\|clk_p_r~clkctrl'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.201 ns" { int_div:inst|clk_p_r int_div:inst|clk_p_r~clkctrl } "NODE_NAME" } } { "int_div.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/int_div.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.666 ns) 7.375 ns jiaotongdeng_con:inst3\|CS.st3 4 REG LCFF_X18_Y8_N17 2 " "Info: 4: + IC(0.840 ns) + CELL(0.666 ns) = 7.375 ns; Loc. = LCFF_X18_Y8_N17; Fanout = 2; REG Node = 'jiaotongdeng_con:inst3\|CS.st3'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.506 ns" { int_div:inst|clk_p_r~clkctrl jiaotongdeng_con:inst3|CS.st3 } "NODE_NAME" } } { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 37.64 % ) " "Info: Total cell delay = 2.776 ns ( 37.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.599 ns ( 62.36 % ) " "Info: Total interconnect delay = 4.599 ns ( 62.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.375 ns" { clock int_div:inst|clk_p_r int_div:inst|clk_p_r~clkctrl jiaotongdeng_con:inst3|CS.st3 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.375 ns" { clock {} clock~combout {} int_div:inst|clk_p_r {} int_div:inst|clk_p_r~clkctrl {} jiaotongdeng_con:inst3|CS.st3 {} } { 0.000ns 0.000ns 1.558ns 2.201ns 0.840ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.357 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns clr 1 PIN PIN_74 4 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_74; Fanout = 4; PIN Node = 'clr'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "jiaotongdeng.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng.bdf" { { 352 48 216 368 "clr" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.919 ns) + CELL(0.366 ns) 8.249 ns jiaotongdeng_con:inst3\|CS~213 2 COMB LCCOMB_X18_Y8_N16 1 " "Info: 2: + IC(6.919 ns) + CELL(0.366 ns) = 8.249 ns; Loc. = LCCOMB_X18_Y8_N16; Fanout = 1; COMB Node = 'jiaotongdeng_con:inst3\|CS~213'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.285 ns" { clr jiaotongdeng_con:inst3|CS~213 } "NODE_NAME" } } { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.357 ns jiaotongdeng_con:inst3\|CS.st3 3 REG LCFF_X18_Y8_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.357 ns; Loc. = LCFF_X18_Y8_N17; Fanout = 2; REG Node = 'jiaotongdeng_con:inst3\|CS.st3'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { jiaotongdeng_con:inst3|CS~213 jiaotongdeng_con:inst3|CS.st3 } "NODE_NAME" } } { "jiaotongdeng_con.v" "" { Text "C:/Documents and Settings/Administrator/桌面/jiaotongdeng/jiaotongdeng_con.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.438 ns ( 17.21 % ) " "Info: Total cell delay = 1.438 ns ( 17.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.919 ns ( 82.79 % ) " "Info: Total interconnect delay = 6.919 ns ( 82.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.357 ns" { clr jiaotongdeng_con:inst3|CS~213 jiaotongdeng_con:inst3|CS.st3 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.357 ns" { clr {} clr~combout {} jiaotongdeng_con:inst3|CS~213 {} jiaotongdeng_con:inst3|CS.st3 {} } { 0.000ns 0.000ns 6.919ns 0.000ns } { 0.000ns 0.964ns 0.366ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.375 ns" { clock int_div:inst|clk_p_r int_div:inst|clk_p_r~clkctrl jiaotongdeng_con:inst3|CS.st3 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.375 ns" { clock {} clock~combout {} int_div:inst|clk_p_r {} int_div:inst|clk_p_r~clkctrl {} jiaotongdeng_con:inst3|CS.st3 {} } { 0.000ns 0.000ns 1.558ns 2.201ns 0.840ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.357 ns" { clr jiaotongdeng_con:inst3|CS~213 jiaotongdeng_con:inst3|CS.st3 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.357 ns" { clr {} clr~combout {} jiaotongdeng_con:inst3|CS~213 {} jiaotongdeng_con:inst3|CS.st3 {} } { 0.000ns 0.000ns 6.919ns 0.000ns } { 0.000ns 0.964ns 0.366ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
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