jiaotongdeng.hif

这程序是利用状态机来控制交通灯verilog码

Version 8.1 Build 163 10/28/2008 SJ Full Version
11
920
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
jiaotongdeng
# storage
db|jiaotongdeng.(0).cnf
db|jiaotongdeng.(0).cnf
# case_insensitive
# source_file
jiaotongdeng.bdf
f714cfb3147e9843fd4b4ac9e376b8
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
jiaotongdeng_con
# storage
db|jiaotongdeng.(1).cnf
db|jiaotongdeng.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jiaotongdeng_con.v
455358daf484e1ef39cbe25b8694c8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
st1
00
PARAMETER_UNSIGNED_BIN
USR
st2
01
PARAMETER_UNSIGNED_BIN
USR
st3
10
PARAMETER_UNSIGNED_BIN
USR
st4
11
PARAMETER_UNSIGNED_BIN
USR
}
# hierarchies {
jiaotongdeng_con:inst3
}
# macro_sequence

# end
# entity
int_div
# storage
db|jiaotongdeng.(2).cnf
db|jiaotongdeng.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
int_div.v
161e85dc24aa080dcc949ddc2aae8af
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
F_DIV
48000000
PARAMETER_UNKNOWN
USR
F_DIV_WIDTH
32
PARAMETER_UNKNOWN
USR
}
# hierarchies {
int_div:inst
}
# macro_sequence

# end
# entity
seg_7
# storage
db|jiaotongdeng.(3).cnf
db|jiaotongdeng.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
seg_7.v
63469ce59072c46e13a5cc61dfd1f8d
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
seg_7:inst4
}
# macro_sequence

# end
# entity
int_div2
# storage
db|jiaotongdeng.(4).cnf
db|jiaotongdeng.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
int_div2.v
6f45a0e6ea0bdfb0558a225cbe1f7
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
F_DIV
100000
PARAMETER_UNKNOWN
USR
F_DIV_WIDTH
32
PARAMETER_UNKNOWN
USR
}
# hierarchies {
int_div2:inst1
}
# macro_sequence

# end
# complete